公开(公告)号：US20110087809A1

公开(公告)日：2011-04-14

申请号：US12923723

申请日：2010-10-05

申请人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

发明人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

IPC分类号： G06F13/10

CPC分类号： G06F13/362 ,  G06F13/1621 ,  G06F13/1689 ,  G06F13/364

摘要： Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, the interconnect circuitry comprising: at least one input for receiving transaction requests from the at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; at least one path for transmitting the transaction requests between the at least one input and the at least one output; control circuitry for routing said received transaction requests from said at least one input to said at least one output; wherein said control circuitry is configured to respond to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths, by not allowing reordering of at least some of said transactions requests that occur before said barrier transaction request in said stream of transaction requests with respect to at least some of said transaction requests that occur after said barrier transaction request in said stream of transaction requests; wherein said control circuitry comprises a response signal generator, said response signal generator being responsive to receipt of said barrier transaction request to issue a response signal, said response signal indicating to upstream blocking circuitry that any transaction requests delayed in response to said barrier transaction request can be transmitted further.

摘要翻译： 公开了一种用于数据处理设备的互连电路。 所述互连电路被配置为提供数据路由，至少一个发起者设备可经由该路径访问至少一个接收方设备，所述互连电路包括：用于从所述至少一个启动器设备接收事务请求的至少一个输入; 用于向所述至少一个接收设备输出交易请求的至少一个输出; 用于在所述至少一个输入和所述至少一个输出之间传送所述事务请求的至少一个路径; 用于将所述接收的交易请求从所述至少一个输入路由到所述至少一个输出的控制电路; 其中所述控制电路被配置为响应于屏障事务请求，以通过不允许重新排序来保持在通过所述至少一个路径之一的事务请求流内关于所述屏障事务请求的至少一些事务请求的排序 关于在所述事务流请求中发生在所述屏障事务请求之后发生的所述事务请求中的至少一些的所述事务请求流中的所述屏障事务请求之前发生的所述事务请求中的至少一些; 其中所述控制电路包括响应信号发生器，所述响应信号发生器响应于接收到所述屏障事务请求以发出响应信号，所述响应信号向上游阻塞电路指示响应于所述屏障事务请求而延迟的任何事务请求可以 进一步传播。

公开(公告)号：US07599998B2

公开(公告)日：2009-10-06

申请号：US10885240

申请日：2004-07-07

申请人： Mark James Galbraith ,  Harry Samuel Thomas Fearnhamm ,  Nicholas Esca Smith ,  Bruce James Mathewson

发明人： Mark James Galbraith ,  Harry Samuel Thomas Fearnhamm ,  Nicholas Esca Smith ,  Bruce James Mathewson

IPC分类号： G06F15/167 ,  G06F15/76

CPC分类号： G06F15/17

摘要： A data processing apparatus comprises at least one source processor core, at least two destination processor cores, a message handler and a bus arrangement providing a data communication path between the source core, the destination cores and the message handler. The message handler has plurality of message-handling modules. At least one of the message-handling modules has a message receipt indicator that is modifiable by each of the destination processor cores to indicate that a message has been received at its destination. This message-handling module also has a transmission completion detector operable to detect, in dependence upon a message receipt indicator value that a message has been received by all of the at least two destination processor cores and to initiate transmission of an acknowledgement signal to the source processor core.

摘要翻译： 数据处理装置包括至少一个源处理器核心，至少两个目的处理器核心，消息处理器和总线装置，其提供源核心，目标核心和消息处理器之间的数据通信路径。 消息处理程序具有多个消息处理模块。 消息处理模块中的至少一个具有可由每个目的处理器核心修改以指示在其目的地已经接收到消息的消息接收指示符。 该消息处理模块还具有传输完成检测器，其可操作用于根据消息接收指示符值来检测消息已被所有至少两个目的处理器核心中的所有接收器接收并且发起确认信号到源 处理器核心。