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31.发明授权Method for ensuring fairness among requests within a multi-node computer system 有权确保多节点计算机系统内的请求之间的公平性的方法公开(公告)号：US07523267B2
公开(公告)日：2009-04-21
申请号：US11532156
申请日：2006-09-15
IPC分类号： G06F13/00
CPC分类号： G06F12/084 , G06F12/0815
摘要： A method to use of dual valid bit sets including a regular bit set and alternate valid bits set which prevents new requests to a given cache line from entering a multi-nodal computer systems' nest system until all requests to the given cache line have been completed successfully. By providing the alternate valid bits the dual set of resource valids for each remote requester is provided for each remote requester, where one set of valids indicates if the resource is valid and actively working on the line, and the other set of valids indicates if the resource was valid but encountered some conflict that requires resolution before the request can complete. Only on successful reload and completion of the remote operation does this alternate address valid bit reset and open the way for any pending interface requests to proceed, so all outstanding requests currently loaded in a local resource within the nest system are able to complete before new interface requests are allowed into the system.
摘要翻译： 使用包括常规位集合和备用有效位集合的双重有效位集合的方法，其阻止对给定高速缓存行的新请求进入多节点计算机系统的嵌套系统，直到对给定高速缓存行的所有请求已经完成为止 成功了 通过提供替代的有效位，为每个远程请求者提供用于每个远程请求者的两组资源代码，其中一组代码指示资源是否有效并且在该行上主动地工作，而另一组代码指示是否 资源有效，但在请求完成之前遇到一些需要解决的冲突。 只有在成功重新加载和完成远程操作时，这个备用地址有效位复位，并为任何待处理的接口请求继续进行打开方式，因此当前加载到嵌套系统中的本地资源的所有未完成的请求都可以在新界面之前完成 请求被允许进入系统。
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公开(公告)号：US07111130B2
公开(公告)日：2006-09-19
申请号：US11402599
申请日：2006-04-12
IPC分类号： G06F12/00
CPC分类号： G06F12/0813 , G06F12/0831
摘要： A shared memory symmetrical processing system including a plurality of nodes each having a system control element for routing internodal communications. A first ring and a second ring interconnect the plurality of nodes, wherein data in said first ring flows in opposite directions with respect to said second ring. A receiver receives a plurality of incoming messages via the first or second ring and merges a plurality of incoming message responses with a local outgoing message response to provide a merged response. Each of the plurality of nodes includes any combination of the following: at least one processor, cache memory, a plurality of I/O adapters, and main memory. The system control element includes a plurality of controllers for maintaining coherency in the system.
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公开(公告)号：US06738871B2
公开(公告)日：2004-05-18
申请号：US09745830
申请日：2000-12-22
IPC分类号： G06F1200
CPC分类号： G06F15/17381
摘要： A remote resource management system for managing resources in a symmetrical multiprocessing environment having a plurality of clusters of symmetric multiprocessors each of which provides interfaces between cluster nodes of the symmetric multiprocessor system with a local interface and an interface controller. One or more remote storage controllers each has a local interface controller and a local-to-remote data bus. A remote fetch controller is responsible for processing data accesses in accordance with the methods described.
摘要翻译： 一种用于在具有多个对称多处理器群集的对称多处理环境中管理资源的远程资源管理系统，每个处理器集群在对称多处理器系统的群集节点与本地接口和接口控制器之间提供接口。 一个或多个远程存储控制器各自具有本地接口控制器和本地到远程的数据总线。 远程提取控制器负责根据所述方法处理数据访问。
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公开(公告)号：US08688880B2
公开(公告)日：2014-04-01
申请号：US12821933
申请日：2010-06-23
CPC分类号： G06F9/526 , G06F2209/522
摘要： Serializing instructions in a multiprocessor system includes receiving a plurality of processor requests at a central point in the multiprocessor system. Each of the plurality of processor requests includes a needs register having a requestor needs switch and a resource needs switch. The method also includes establishing a tail switch indicating the presence of the plurality of processor requests at the central point, establishing a sequential order of the plurality of processor requests, and processing the plurality of processor requests at the central point in the sequential order.
摘要翻译： 在多处理器系统中串行化指令包括在多处理器系统的中心点处接收多个处理器请求。 多个处理器请求中的每一个包括具有请求者需求切换和资源需要切换的需求寄存器。 该方法还包括建立指示在中心点存在多个处理器请求的尾部开关，建立多个处理器请求的顺序，以及按照顺序在中心点处理多个处理器请求。
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公开(公告)号：US20110320778A1
公开(公告)日：2011-12-29
申请号：US12821933
申请日：2010-06-23
IPC分类号： G06F9/30
CPC分类号： G06F9/526 , G06F2209/522
摘要： Serializing instructions in a multiprocessor system includes receiving a plurality of processor requests at a central point in the multiprocessor system. Each of the plurality of processor requests includes a needs register having a requestor needs switch and a resource needs switch. The method also includes establishing a tail switch indicating the presence of the plurality of processor requests at the central point, establishing a sequential order of the plurality of processor requests, and processing the plurality of processor requests at the central point in the sequential order.
摘要翻译： 在多处理器系统中串行化指令包括在多处理器系统的中心点处接收多个处理器请求。 多个处理器请求中的每一个包括具有请求者需求切换和资源需要切换的需求寄存器。 该方法还包括建立指示在中心点存在多个处理器请求的尾部开关，建立多个处理器请求的顺序，以及按照顺序在中心点处理多个处理器请求。
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36.发明授权Horizontal cache persistence in a multi-compute node, symmetric multiprocessing computer 失效多计算节点，对称多处理计算机中的水平缓存持久性公开(公告)号：US08364904B2
公开(公告)日：2013-01-29
申请号：US12819348
申请日：2010-06-21
申请人： Michael A. Blake , Lawrence D. Curley , Garrett M. Drapala , Edward J. Kaminski , Craig R. Walters
发明人： Michael A. Blake , Lawrence D. Curley , Garrett M. Drapala , Edward J. Kaminski , Craig R. Walters
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F12/084
摘要： Horizontal cache persistence in a multi-compute node, SMP computer, including, responsive to a determination to evict a cache line on a first one of the compute nodes, broadcasting by a first compute node an eviction notice for the cache line; transmitting the state of the cache line receiving compute nodes, including, if the cache line is missing from a compute node, an indication whether that compute node has cache storage space available for the cache line; determining by the first compute node, according to the states of the cache line and space available, whether the first compute node can evict the cache line without writing the cache line to main memory; and updating by each compute node the state of the cache line in each compute node, in dependence upon one or more of the states of the cache line in all the compute nodes.
摘要翻译： 包括在多计算节点SMP计算机中的水平缓存持续性，包括响应于在计算节点的第一个计算节点上驱逐高速缓存行的确定，由第一计算节点广播高速缓存行的逐出通知; 发送接收计算节点的高速缓存行的状态，包括如果高速缓存线从计算节点丢失，则指示该计算节点是否具有可用于高速缓存行的高速缓存存储空间; 由所述第一计算节点根据所述高速缓存行的状态和可用空间来确定所述第一计算节点是否可以驱逐所述高速缓存行而不将高速缓存行写入主存储器; 并且根据所有计算节点中的高速缓存行的一个或多个状态，由每个计算节点更新每个计算节点中的高速缓存行的状态。
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37.发明申请Horizontal Cache Persistence In A Multi-Compute Node, Symmetric Multiprocessing Computer 失效多计算节点中的水平缓存持久性，对称多处理计算机公开(公告)号：US20110314227A1
公开(公告)日：2011-12-22
申请号：US12819348
申请日：2010-06-21
申请人： Michael A. Blake , Lawrence D. Curley , Garrett M. Drapala , Edward J. Kaminski, JR. , Craig R. Walters
发明人： Michael A. Blake , Lawrence D. Curley , Garrett M. Drapala , Edward J. Kaminski, JR. , Craig R. Walters
IPC分类号： G06F12/08
CPC分类号： G06F12/127 , G06F12/084
摘要： Horizontal cache persistence in a multi-compute node, SMP computer, including, responsive to a determination to evict a cache line on a first one of the compute nodes, broadcasting by a first compute node an eviction notice for the cache line; transmitting the state of the cache line receiving compute nodes, including, if the cache line is missing from a compute node, an indication whether that compute node has cache storage space available for the cache line; determining by the first compute node, according to the states of the cache line and space available, whether the first compute node can evict the cache line without writing the cache line to main memory; and updating by each compute node the state of the cache line in each compute node, in dependence upon one or more of the states of the cache line in all the compute nodes.
摘要翻译： 包括在多计算节点SMP计算机中的水平缓存持续性，包括响应于在计算节点的第一个计算节点上驱逐高速缓存行的确定，由第一计算节点广播高速缓存行的逐出通知; 发送接收计算节点的高速缓存行的状态，包括如果高速缓存线从计算节点丢失，则指示该计算节点是否具有可用于高速缓存行的高速缓存存储空间; 由所述第一计算节点根据所述高速缓存行的状态和可用空间来确定所述第一计算节点是否可以驱逐所述高速缓存行而不将高速缓存行写入主存储器; 并且根据所有计算节点中的高速缓存行的一个或多个状态，由每个计算节点更新每个计算节点中的高速缓存行的状态。
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公开(公告)号：US08788891B2
公开(公告)日：2014-07-22
申请号：US13523633
申请日：2012-06-14
申请人： Ekaterina M. Ambroladze , Michael A. Blake , Michael Fee , Hieu T. Huynh , Patrick J. Meaney , Arthur J. O'Neill
发明人： Ekaterina M. Ambroladze , Michael A. Blake , Michael Fee , Hieu T. Huynh , Patrick J. Meaney , Arthur J. O'Neill
CPC分类号： G06F11/1064 , G06F11/073 , G06F11/076 , G06F11/08 , G11C2029/1204
摘要： Embodiments relate to a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line and recording a second address of the second error. Embodiments also include comparing the first and second bitline address, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching the first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to a third bitline address and deleting a location corresponding to the third cache line from available cache locations based on the activated bitline delete mode and the third bitline address matching the second bitline address.
摘要翻译： 实施例涉及一种方法，包括当读取第一高速缓存行时检测第一错误，记录第一错误的第一地址，在读取第二高速缓存行时检测第二错误并记录第二错误的第二地址。 实施例还包括比较第一和第二位线地址，比较第一和第二字线地址，基于匹配的第一和第二位线地址激活位线删除模式，并且不匹配第一和第二字线地址，在读取第三位线时检测第三错误 记录第三错误的第三位线地址，将第二位线地址与第三位线地址进行比较，并且基于激活的位线删除模式和第三位线地址匹配从可用高速缓存位置删除与第三高速缓存行相对应的位置 第二个位线地址。
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39.发明授权Dynamic cache correction mechanism to allow constant access to addressable index 失效动态高速缓存校正机制，允许持续访问可寻址索引公开(公告)号：US08719618B2
公开(公告)日：2014-05-06
申请号：US13495174
申请日：2012-06-13
IPC分类号： G06F11/00
CPC分类号： G06F11/073 , G06F11/0757 , G06F11/20 , G06F12/08 , G06F12/0811 , G06F12/0864 , G06F12/126 , G06F2212/1032
摘要： A technique is provided for a cache. A cache controller accesses a set in a congruence class and determines that the set contains corrupted data based on an error being found. The cache controller determines that a delete parameter for taking the set offline is met and determines that a number of currently offline sets in the congruence class is higher than an allowable offline number threshold. The cache controller determines not to take the set in which the error was found offline based on determining that the number of currently offline sets in the congruence class is higher than the allowable offline number threshold.
摘要翻译： 为缓存提供了一种技术。 高速缓存控制器访问同余类中的集合，并根据发现的错误确定该集合包含损坏的数据。 高速缓存控制器确定满足设置离线的删除参数，并确定同余类中当前离线集合的数量高于允许的离线号码阈值。 缓存控制器根据确定同余类中当前离线集合的数量高于允许的离线号码阈值，确定不采取脱机发生的集合。
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公开(公告)号：US08333421B2
公开(公告)日：2012-12-18
申请号：US13052224
申请日：2011-03-21
IPC分类号： B60N2/02
CPC分类号： B60N2/01583 , B60N2/01591
摘要： A vehicle seat front floor latch and positioner assembly (26) for a rear vehicle seat (10) movable between a seating position, a generally horizontal nonuse position, and a generally vertical storage position as well as being removable from the vehicle to increase cargo capacity.
摘要翻译： 一种用于后车辆座椅（10）的车辆座椅前地板闩锁和定位器组件（26），其可在就座位置，大体上水平的不使用位置和大致垂直的存储位置之间移动，并且可从车辆移除以增加货物容量 。
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