公开(公告)号：US08788891B2

公开(公告)日：2014-07-22

申请号：US13523633

申请日：2012-06-14

申请人： Ekaterina M. Ambroladze ,  Michael A. Blake ,  Michael Fee ,  Hieu T. Huynh ,  Patrick J. Meaney ,  Arthur J. O'Neill

发明人： Ekaterina M. Ambroladze ,  Michael A. Blake ,  Michael Fee ,  Hieu T. Huynh ,  Patrick J. Meaney ,  Arthur J. O'Neill

IPC分类号： G06F11/00 ,  G11C29/00 ,  G06F11/10 ,  G11C29/12

CPC分类号： G06F11/1064 ,  G06F11/073 ,  G06F11/076 ,  G06F11/08 ,  G11C2029/1204

摘要： Embodiments relate to a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line and recording a second address of the second error. Embodiments also include comparing the first and second bitline address, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching the first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to a third bitline address and deleting a location corresponding to the third cache line from available cache locations based on the activated bitline delete mode and the third bitline address matching the second bitline address.

摘要翻译： 实施例涉及一种方法，包括当读取第一高速缓存行时检测第一错误，记录第一错误的第一地址，在读取第二高速缓存行时检测第二错误并记录第二错误的第二地址。 实施例还包括比较第一和第二位线地址，比较第一和第二字线地址，基于匹配的第一和第二位线地址激活位线删除模式，并且不匹配第一和第二字线地址，在读取第三位线时检测第三错误 记录第三错误的第三位线地址，将第二位线地址与第三位线地址进行比较，并且基于激活的位线删​​除模式和第三位线地址匹配从可用高速缓存位置删除与第三高速缓存行相对应的位置 第二个位线地址。

公开(公告)号：US20130339808A1

公开(公告)日：2013-12-19

申请号：US13523633

申请日：2012-06-14

申请人： Ekaterina M. Ambroladze ,  Michael A. Blake ,  Michael Fee ,  Hieu T. Huynh ,  Patrick J. Meaney ,  Arthur J. O'Neill

发明人： Ekaterina M. Ambroladze ,  Michael A. Blake ,  Michael Fee ,  Hieu T. Huynh ,  Patrick J. Meaney ,  Arthur J. O'Neill

IPC分类号： G06F11/20

CPC分类号： G06F11/1064 ,  G06F11/073 ,  G06F11/076 ,  G06F11/08 ,  G11C2029/1204

摘要： Embodiments relate to a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line and recording a second address of the second error. Embodiments also include comparing the first and second bitline address, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching the first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to a third bitline address and deleting a location corresponding to the third cache line from available cache locations based on the activated bitline delete mode and the third bitline address matching the second bitline address.

摘要翻译： 实施例涉及一种方法，包括当读取第一高速缓存行时检测第一错误，记录第一错误的第一地址，在读取第二高速缓存行时检测第二错误并记录第二错误的第二地址。 实施例还包括比较第一和第二位线地址，比较第一和第二字线地址，基于匹配的第一和第二位线地址激活位线删除模式，并且不匹配第一和第二字线地址，在读取第三位线时检测第三错误 记录第三错误的第三位线地址，将第二位线地址与第三位线地址进行比较，并且基于激活的位线删​​除模式和第三位线地址匹配从可用高速缓存位置删除与第三高速缓存行相对应的位置 第二个位线地址。

公开(公告)号：US09003125B2

公开(公告)日：2015-04-07

申请号：US13523535

申请日：2012-06-14

申请人： Ekaterina M. Ambroladze ,  Michael Blake ,  Tim Bronson ,  Garrett Drapala ,  Pak-kin Mak ,  Arthur J. O'Neill

发明人： Ekaterina M. Ambroladze ,  Michael Blake ,  Tim Bronson ,  Garrett Drapala ,  Pak-kin Mak ,  Arthur J. O'Neill

IPC分类号： G06F12/08

CPC分类号： G06F12/0891 ,  G06F12/0815 ,  G06F12/0859

摘要： A technique for cache coherency is provided. A cache controller selects a first set from multiple sets in a congruence class based on a cache miss for a first transaction, and places a lock on the entire congruence class in which the lock prevents other transactions from accessing the congruence class. The cache controller designates in a cache directory the first set with a marked bit indicating that the first transaction is working on the first set, and the marked bit for the first set prevents the other transactions from accessing the first set within the congruence class. The cache controller removes the lock on the congruence class based on the marked bit being designated for the first set, and resets the marked bit for the first set to an unmarked bit based on the first transaction completing work on the first set in the congruence class.

摘要翻译： 提供了高速缓存一致性技术。 高速缓存控制器基于第一事务的高速缓存未命中从一个等同类中的多个集合中选择第一集合，并且将锁定放置在整个一致类中，其中锁定防止其他事务访问同余类。 高速缓存控制器在高速缓存目录中指定具有指示第一事务在第一集合上工作的标记位的第一集合，并且第一集合的标记位阻止其他事务访问同余类中的第一集合。 高速缓存控制器基于为第一组指定的标记位移除同余类上的锁，并且基于在一致类中的第一集合上的第一次交易完成工作将第一组的标记位重置为未标记位 。

公开(公告)号：US20130339622A1

公开(公告)日：2013-12-19

申请号：US13523535

申请日：2012-06-14

申请人： Ekaterina M. Ambroladze ,  Michael Blake ,  Tim Bronson ,  Garrett Drapala ,  Pak-kin Mak ,  Arthur J. O'Neill

发明人： Ekaterina M. Ambroladze ,  Michael Blake ,  Tim Bronson ,  Garrett Drapala ,  Pak-kin Mak ,  Arthur J. O'Neill

IPC分类号： G06F12/08

CPC分类号： G06F12/0891 ,  G06F12/0815 ,  G06F12/0859

摘要： A technique for cache coherency is provided. A cache controller selects a first set from multiple sets in a congruence class based on a cache miss for a first transaction, and places a lock on the entire congruence class in which the lock prevents other transactions from accessing the congruence class. The cache controller designates in a cache directory the first set with a marked bit indicating that the first transaction is working on the first set, and the marked bit for the first set prevents the other transactions from accessing the first set within the congruence class. The cache controller removes the lock on the congruence class based on the marked bit being designated for the first set, and resets the marked bit for the first set to an unmarked bit based on the first transaction completing work on the first set in the congruence class.

摘要翻译： 提供了高速缓存一致性技术。 高速缓存控制器基于第一事务的高速缓存未命中从一个等同类中的多个集合中选择第一集合，并且将锁定放置在整个一致类中，其中锁定防止其他事务访问同余类。 高速缓存控制器在高速缓存目录中指定具有指示第一事务在第一集合上工作的标记位的第一集合，并且第一集合的标记位阻止其他事务访问同余类中的第一集合。 高速缓存控制器基于为第一组指定的标记位移除同余类上的锁，并且基于在一致类中的第一集合上的第一次交易完成工作将第一组的标记位重置为未标记位 。

公开(公告)号：US20130339822A1

公开(公告)日：2013-12-19

申请号：US13523971

申请日：2012-06-15

申请人： Patrick J. Meaney ,  Arthur J. O'Neill ,  Gary E. Strait

发明人： Patrick J. Meaney ,  Arthur J. O'Neill ,  Gary E. Strait

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/05 ,  G06F11/073 ,  G06F11/1008 ,  G06F11/1064 ,  G06F11/1666 ,  G06F11/20

摘要： A technique for error detection is provided. A controller is configured to detect errors by using error correcting code (ECC), and a cache includes independent ECC words for storing data. The controller detects the errors in the ECC words for a wordline that is read. The controller detects a first error in a first ECC word on the wordline and a second error in a second ECC word on the wordline. The controller determines that the wordline is a failing wordline based on detecting the first error in the first ECC word and the second error in the second ECC word.

公开(公告)号：US07502986B2

公开(公告)日：2009-03-10

申请号：US11054575

申请日：2005-02-09

申请人： Arthur J. O'Neill ,  Patrick J. Meaney

发明人： Arthur J. O'Neill ,  Patrick J. Meaney

IPC分类号： H03M13/00

CPC分类号： G06F11/10

摘要： A method of error correction code (ECC) debugging for a system comprising, receiving data having an ECC, determining whether a data error has occurred, generating a syndrome of an error result, decoding flipped data bits, processing the received data and the decoded flipped bits to correct the data, outputting corrected data having an ECC, receiving a trap update signal, and saving the decoded flipped data bits responsive to receiving the trap update signal.

摘要翻译： 一种用于系统的纠错码（ECC）调试的方法，包括：接收具有ECC的数据，确定是否已经发生数据错误，产生错误结果的综合征，翻转翻转的数据位，处理接收的数据和解码的翻转的 位校正数据，输出具有ECC的校正数据，接收陷阱更新信号，以及响应于接收到陷阱更新信号而保存解码翻转数据位。

公开(公告)号：US08914708B2

公开(公告)日：2014-12-16

申请号：US13523971

申请日：2012-06-15

申请人： Patrick J. Meaney ,  Arthur J. O'Neill ,  Gary E. Strait

发明人： Patrick J. Meaney ,  Arthur J. O'Neill ,  Gary E. Strait

IPC分类号： G11C29/00 ,  H03M13/05 ,  G06F11/07 ,  G06F11/10

CPC分类号： H03M13/05 ,  G06F11/073 ,  G06F11/1008 ,  G06F11/1064 ,  G06F11/1666 ,  G06F11/20

摘要： A technique for error detection is provided. A controller is configured to detect errors by using error correcting code (ECC), and a cache includes independent ECC words for storing data. The controller detects the errors in the ECC words for a wordline that is read. The controller detects a first error in a first ECC word on the wordline and a second error in a second ECC word on the wordline. The controller determines that the wordline is a failing wordline based on detecting the first error in the first ECC word and the second error in the second ECC word.

摘要翻译： 提供了一种错误检测技术。 控制器被配置为通过使用纠错码（ECC）来检测错误，并且高速缓存包括用于存储数据的独立ECC字。 控制器检测读取的字线的ECC字中的错误。 控制器检测字线上的第一ECC字中的第一错误和字线上的第二ECC字中的第二错误。 控制器基于检测第一ECC字中的第一错误和第二ECC字中的第二错误，确定字线是故障字线。

公开(公告)号：US08316284B2

公开(公告)日：2012-11-20

申请号：US12360402

申请日：2009-01-27

申请人： Arthur J. O'Neill ,  Patrick J. Meaney

发明人： Arthur J. O'Neill ,  Patrick J. Meaney

IPC分类号： H03M13/00 ,  G11C29/00

CPC分类号： G06F11/10

摘要： Methods of error correction code (ECC) debugging may comprise detecting whether a bit error has occurred; determining which bit or bits were in error; and using the bit error information for debug. The method may further comprise comparing ECC syndromes against one or more ECC syndrome patterns. The method may allow for accumulating bit error information, comparing error bit failures against a pattern, trapping data, counting errors, determining pick/drop information, or stopping the machine for debug.

摘要翻译： 纠错码（ECC）调试方法可以包括检测是否发生位错误; 确定哪些位或位是错误的; 并使用位错误信息进行调试。 该方法还可以包括比较ECC综合征与一个或多个ECC综合征模式。 该方法可以允许累积位错误信息，将错误位故障与模式进行比较，捕获数据，计数错误，确定拾取/丢弃信息或停止机器进行调试。

公开(公告)号：US20090164874A1

公开(公告)日：2009-06-25

申请号：US12360402

申请日：2009-01-27

申请人： Arthur J. O'Neill ,  Patrick J. Meaney

发明人： Arthur J. O'Neill ,  Patrick J. Meaney

IPC分类号： H03M13/15 ,  G06F11/10

CPC分类号： G06F11/10

摘要： Methods and means of error correction code (ECC) debugging may comprise detecting whether a bit error has occurred; determining which bit or bits were in error; and using the bit error information for debug. The method may further comprise comparing ECC syndromes against one or more ECC syndrome patterns. The method may allow for accumulating bit error information, comparing error bit failures against a pattern, trapping data, counting errors, determining pick/drop information, or stopping the machine for debug.

摘要翻译： 纠错码（ECC）调试的方法和手段可以包括检测是否发生位错误; 确定哪些位或位是错误的; 并使用位错误信息进行调试。 该方法还可以包括比较ECC综合征与一个或多个ECC综合征模式。 该方法可以允许累积位错误信息，将错误位故障与模式进行比较，捕获数据，计数错误，确定拾取/丢弃信息或停止机器进行调试。

公开(公告)号：US08131937B2

公开(公告)日：2012-03-06

申请号：US11766977

申请日：2007-06-22

申请人： Michael A. Blake ,  Harmony L. Helterhoff ,  Arthur J. O'Neill ,  Vesselina K. Papazova ,  Craig R. Walters

发明人： Michael A. Blake ,  Harmony L. Helterhoff ,  Arthur J. O'Neill ,  Vesselina K. Papazova ,  Craig R. Walters

IPC分类号： G06F13/00

CPC分类号： G06F12/084 ,  G06F12/0897 ,  G06F12/126

摘要： Improved access to retained data useful to a system is accomplished by managing data flow through cache associated with the processor(s) of a multi-node system. A data management facility operable with the processors and memory array directs the flow of data from the processors to the memory array by determining the path along which data evicted from a level of cache close to one of the processors is to return to a main memory and directing evicted data to be stored, if possible, in a horizontally associated cache.

摘要翻译： 改进对对系统有用的保留数据的访问通过管理与多节点系统的处理器相关联的高速缓存的数据流来实现。 可与处理器和存储器阵列一起操作的数据管理设备通过确定沿着哪个数据从处理器中的一个接收到的高速缓存驱逐出的数据返回到主存储器，从而将来自处理器的数据流引导到存储器阵列， 如果可能的话，将被驱逐的数据存储在水平相关的缓存中。