公开(公告)号：US4208727A

公开(公告)日：1980-06-17

申请号：US915633

申请日：1978-06-15

Applicant: Donald J. Redwine ,  G. R. Mohan Rao

Inventor： Donald J. Redwine ,  G. R. Mohan Rao

IPC: G11C17/08 ,  G11C17/12 ,  G11C17/06

CPC classification number: G11C17/08 ,  G11C17/12 ,  Y10S148/055 ,  Y10S257/926

Abstract: A semiconductor integrated circuit functioning as a read only memory or ROM employs MOS diodes as the memory cells and is formed by a process compatible with standard N-channel silicon gate manufacturing methods. Row address lines are metal strips and gates are polysilicon segments, while output or column lines are defined by elongated N+ regions. The gates are shorted to N+ drain regions to provide diode-like cells. Each MOS transistor in the array is programmed to be a logic "1" or "0", such as by ion implanting through the polysilicon gates and thin gate oxide, rendering some cells of such high threshold that they will not turn on. Alternatively, the array may be contact programmable.

Abstract translation: 用作只读存储器或ROM的半导体集成电路使用MOS二极管作为存储单元，并且通过与标准N沟道硅栅极制造方法兼容的工艺形成。 行地址线是金属条，栅极是多晶硅段，而输出或列线由细长N +区限定。 栅极与N +漏极区短接，以提供二极管状电池。 阵列中的每个MOS晶体管被编程为逻辑“1”或“0”，例如通过离子注入通过多晶硅栅极和薄栅极氧化物，使一些电池具有这样高的阈值，使得它们不会导通。 或者，阵列可以是可编程的。