公开(公告)号：US20080220607A1

公开(公告)日：2008-09-11

申请号：US12123701

申请日：2008-05-20

Applicant: Klaus Hummler

Inventor： Klaus Hummler

IPC: H01L21/44 ,  H01L21/70 ,  G11C5/06

CPC classification number: H01L23/3114 ,  H01L23/525 ,  H01L2924/0002 ,  Y10S257/926 ,  H01L2924/00

Abstract: A method of routing signals within a semiconductor memory device includes providing a semiconductor wafer having a top surface with a center portion, an edge portion and wafer bond pads at the center portion. A redistribution layer is provided on the top surface of the semiconductor wafer. The method includes redistributing signals from the wafer bond pads to redistribution edge pads utilizing the redistribution layer, and routing signals from the semiconductor wafer up to the redistribution layer and routing these signals back down to the semiconductor wafer.

Abstract translation: 一种在半导体存储器件内路由信号的方法包括提供具有中心部分的顶表面的半导体晶片，在中心部分具有边缘部分和晶片接合焊盘。 在半导体晶片的顶表面上设置再分布层。 该方法包括重新分配来自晶片接合焊盘的信号，以利用再分配层重新分配边缘焊盘，以及将信号从半导体晶片转移到再分布层并将这些信号路由到半导体晶片。

公开(公告)号：US07391107B2

公开(公告)日：2008-06-24

申请号：US11206481

申请日：2005-08-18

Applicant: Klaus Hummler

Inventor： Klaus Hummler

IPC: H01L23/48

CPC classification number: H01L23/3114 ,  H01L23/525 ,  H01L2924/0002 ,  Y10S257/926 ,  H01L2924/00

Abstract: A semiconductor wafer has a dielectric layer, a metal last layer, a passivation layer, and a redistribution layer. The metal last layer is formed over the dielectric layer, and the metal last layer has first and second locations that are spaced apart from each other. The passivation layer is formed over the metal last layer. The redistribution layer is formed over the passivation layer. The redistribution layer has a signal routing wire coupled to the first location of the metal last layer and to the second location of the metal last layer.

Abstract translation: 半导体晶片具有电介质层，金属最后层，钝化层和再分配层。 金属最后层形成在电介质层上，并且金属最后层具有彼此间隔开的第一和第二位置。 钝化层形成在金属最后层上。 再分布层形成在钝化层上。 再分布层具有耦合到金属最后层的第一位置和金属最后层的第二位置的信号布线。

公开(公告)号：US5907778A

公开(公告)日：1999-05-25

申请号：US907020

申请日：1997-08-06

Applicant: Jih-Wen Chou ,  Jemmy Wen

Inventor： Jih-Wen Chou ,  Jemmy Wen

IPC: H01L21/8229 ,  H01L27/102 ,  H01L21/8246

CPC classification number: H01L21/8229 ,  H01L27/1021 ,  Y10S257/926

Abstract: A method is provided for fabricating a read-only memory (ROM) device of the type including an array of diode-based memory cells for permanent storage of binary-coded data. The ROM device is partitioned into a memory division and an output division. The memory cells are formed over an insulating layer in the memory division. The insulating layer separates the memory cells from the underlying substrate such that the leakage current that can otherwise occur therebetween can be prevented. Moreover, the coding process is performing by forming contact windows at selected locations rather than by performing ion-implantation as in conventional methods. The fabrication process is thus easy to perform. Since the memory cells are diode-based rather than MOSFET-based, the punch-through effect that usually occurs in MOSFET-based memory cells can be prevented. The diode-based structure also allows the packing density of the memory cells on the ROM device to be dependent on the line width of the polysilicon layers in the ROM device. The feature size of the ROM device is thus dependent on the capability of the photolithographic process.

Abstract translation: 提供了一种用于制造这种类型的只读存储器（ROM）器件的方法，该器件包括用于永久存储二进制编码数据的基于二极管的存储器单元阵列。 ROM设备被划分为存储器部分和输出部分。 存储器单元形成在存储器分区中的绝缘层上。 绝缘层将存储器单元与下层衬底分离，从而可以防止其间发生的泄漏电流。 此外，编码过程是通过在所选位置形成接触窗而不是按照常规方法进行离子注入而进行的。 因此制造工艺容易执行。 由于存储器单元是基于二极管的而不是基于MOSFET的，所以可以防止通常发生在基于MOSFET的存储器单元中的穿透效应。 基于二极管的结构还允许ROM器件上的存储器单元的堆积密度取决于ROM器件中多晶硅层的线宽。 因此ROM器件的特征尺寸取决于光刻工艺的能力。

公开(公告)号：US5580809A

公开(公告)日：1996-12-03

申请号：US492217

申请日：1995-06-19

Applicant: Shinichi Mori ,  Osamu Ueda ,  Masayuki Yamashita

Inventor： Shinichi Mori ,  Osamu Ueda ,  Masayuki Yamashita

IPC: G11C11/56 ,  H01L21/8246 ,  H01L27/112

CPC classification number: G11C11/5692 ,  H01L27/112 ,  Y10S257/926 ,  Y10S438/981

Abstract: Each of the portions corresponding to the crossings of a plurality of first strip conductive layers serving as bit lines and a plurality of second strip conductive layers serving as word lines crossing the conductive layers at right angles is used as one memory cell. An oxide film is provided between the first strip conductive layers and the second strip conductive layers. The thickness of this oxide film is set in each memory cell according to stored data. Also a multi-value memory can be realized, since the amount of stored data in each memory cell is an arbitrary amount of 1 bit or more by making the stored data of a plurality of types of memory cells having different thicknesses in the tunnel oxide film 15 correspond to a plurality of different data. The size of each memory cell can be reduced since the occupying area of each memory cell on the semiconductor substrate is dependent on the width of the first strip conductive layer and the second strip conductive layer. An insulation film in which tunnel phenomenon is generated can be formed using conventional manufacturing technology.

Abstract translation: 作为用作位线的多个第一带状导电层和作为与导电层成直角交叉的字线的多个第二带状导电层的交叉部分的每个部分被用作一个存储单元。 在第一带状导电层和第二带状导电层之间设置氧化膜。 根据存储的数据，将该氧化膜的厚度设定在各存储单元中。 另外，可以实现多值存储器，因为通过在隧道氧化膜中存储具有不同厚度的多种类型的存储单元的存储数据，每个存储单元中存储的数据量是1位或更多的任意量 15对应于多个不同的数据。 由于半导体衬底上的每个存储单元的占有面积取决于第一带状导电层和第二带状导电层的宽度，因此可以减小每个存储单元的尺寸。 可以使用传统的制造技术形成其中产生隧道现象的绝缘膜。

公开(公告)号：US5130760A

公开(公告)日：1992-07-14

申请号：US714113

申请日：1991-06-11

Applicant: Walter T. Matzen ,  Ronald B. Foster

Inventor： Walter T. Matzen ,  Ronald B. Foster

IPC: H01L29/866 ,  H01L27/02

CPC classification number: H01L27/0248 ,  Y10S257/926

Abstract: A semiconductor device is provided for use as a bidirectional surge suppressor circuit. It incorporates doped regions of substrate and epitaxial layers which result in a dual Zener diode arrangement having the Zener diodes associated in an opposite polarity arrangement. The semiconductor device comprises a substrate with an epitaxial layer deposited on one of its surfaces. In an upper surface of the epitaxial layer, first and second regions of P type material are diffused with guard rings comprising P+ type material diffused around the first and second regions. The guard rings are heavily doped and extend much deeper than the relatively shallow junctions of P material. A channel stopper of N+ conductivity type material is diffused into the upper surface of the epitaxial layer to provide a channel stopper, or sinker, around both the first and second regions and their associated guard rings and, additionally, between the first and second regions. This structure provides several significant advantages including reduced current leakage reliability, uniform breakdown voltage, crack resistance and a smaller area needed to provide the required thermal capacity.

公开(公告)号：US5117114A

公开(公告)日：1992-05-26

申请号：US448240

申请日：1989-12-11

Applicant: Robert A. Street ,  Selig N. Kaplan ,  Victor Perez-Mendez

Inventor： Robert A. Street ,  Selig N. Kaplan ,  Victor Perez-Mendez

IPC: G01T1/20 ,  G01T1/24 ,  H01L31/0232 ,  H01L31/117

CPC classification number: H01L31/0232 ,  G01T1/2018 ,  H01L31/02322 ,  H01L31/117 ,  Y10S257/926

Abstract: A radiation detector employing amorphous Si:H cells in an array with each detector cell having at least three contiguous layers (n type, intrinsic, p type), positioned between two electrodes to which a bias voltage is applied. An energy conversion layer atop the silicon cells intercepts incident radiation and converts radiation energy to light energy of a wavelength to which the silicon cells are responsive. A read-out device, positioned proximate to each detector element in an array allows each such element to be interrogated independently to determine whether radiation has been detected in that cell. The energy conversion material may be a layer of luminescent material having a columnar structure. In one embodiment a column of luminescent material detects the passage therethrough of radiation to be detected and directs a light beam signal to an adjacent a-Si:H film so that detection may be confined to one or more such cells in the array. One or both electrodes may have a comb structure, and the teeth of each electrode comb may be interdigitated for capacitance reduction. The amorphous Si:H film may be replaced by an amorphous Si:Ge:H film in which up to 40 percent of the amorphous material is Ge. Two dimensional arrays may be used in X-ray imaging, CT scanning, crystallography, high energy physics beam tracking, nuclear medicine cameras and autoradiography.

Abstract translation: 一种辐射检测器，其采用阵列中的非晶Si：H电池，其中每个检测器单元具有至少三个相邻层（n型，本征型，p型），位于施加有偏置电压的两个电极之间。 硅单元顶部的能量转换层拦截入射辐射，并将辐射能转换成硅单元响应的波长的光能。 位于阵列中的每个检测器元件附近的读出装置允许独立地询问每个这样的元件以确定是否在该单元中检测到辐射。 能量转换材料可以是具有柱状结构的发光材料层。 在一个实施例中，一列发光材料检测待检测的辐射的通过，并将光束信号引导到相邻的a-Si：H膜，使得检测可以局限于阵列中的一个或多个这样的单元。 一个或两个电极可以具有梳状结构，并且每个电极梳的齿可以相互交叉以减少电容。 非晶Si：H膜可以由非晶Si：Ge：H膜替代，其中高达40％的无定形材料是Ge。 二维阵列可用于X射线成像，CT扫描，晶体学，高能物理光束跟踪，核医学相机和放射自显影。

公开(公告)号：US5070383A

公开(公告)日：1991-12-03

申请号：US295274

申请日：1989-01-10

Applicant: Alexander B. Sinar ,  Levy Gerzberg ,  Yosef Y. Shacham ,  Ilan A. Blech ,  Eric R. Sirkin

Inventor： Alexander B. Sinar ,  Levy Gerzberg ,  Yosef Y. Shacham ,  Ilan A. Blech ,  Eric R. Sirkin

IPC: H01L23/525 ,  H01L27/102

CPC classification number: H01L27/1021 ,  H01L23/5252 ,  H01L2924/0002 ,  Y10S257/91 ,  Y10S257/926

Abstract: A memory matrix comprises a plurality of word lines, a plurality of bit lines, and a stacked diode and voltage-variable resistor structure interconnecting bit lines to word lines. The stacked diode and voltage-variable resistor structure includes a doped region in a semiconductor substrate defining a work line, a doped polycrystalline silicon layer over said word line and forming a p-n junction therewith, and an amorphized region in the doped polycrystalline silicon layer having increased resistance over the non-amorphized portion of the doped polycrystalline silicon layer. A contact is made to the amorphized polycrystalline silicon material which preferably includes a titanium-tungsten barrier layer and an aluminum layer over the barrier layer. To improve the breakdown voltage of the diode structure, a region of opposite conductivity type is formed in the word line under the doped polycrystalline silicon layer either by out-diffusion of dopants from the polycrystalline silicon layer or by the implantation of dopant ions through the polycrystalline silicon layer into the word line.

Abstract translation: 存储矩阵包括多个字线，多个位线以及将位线互连到字线的堆叠二极管和电压可变电阻器结构。 层叠二极管和可变电压结构包括在限定工作线的半导体衬底中的掺杂区域，在所述字线上方形成掺杂多晶硅层并与其形成pn结，掺杂多晶硅层中的非晶化区域具有增加的 掺杂多晶硅层非非晶化部分的电阻。 对非晶化多晶硅材料进行接触，其优选在阻挡层上包括钛 - 钨阻挡层和铝层。 为了提高二极管结构的击穿电压，在掺杂多晶硅层下面的字线中形成相反导电类型的区域，通过掺杂剂从多晶硅层的扩散或通过掺杂剂离子注入多晶硅 硅层进入字线。

公开(公告)号：US4868623A

公开(公告)日：1989-09-19

申请号：US161223

申请日：1988-02-17

Applicant: Masaharu Nishiura

Inventor： Masaharu Nishiura

IPC: H01L27/146 ,  H04N1/028

CPC classification number: H01L27/14665 ,  Y10S257/91 ,  Y10S257/926

Abstract: An amorphous silicon thin-film p-i-n photodiode array image sensor structure is provided which avoids excessive leakage currents caused by contamination of the side-walls of anisotropically etched amorphous silicon film with conducting materials, such as metal or metal silicide, during fabrication. The present image sensor structure includes a deposited SiO.sub.2 layer that separates all exposed silicon side-walls from directly underlying conductors.

Abstract translation: 提供了非晶硅薄膜p-i-n光电二极管阵列图像传感器结构，其避免了在制造期间由诸如金属或金属硅化物的导电材料污染各向异性蚀刻的非晶硅膜的侧壁引起的过度的漏电流。 本图像传感器结构包括沉积的SiO 2层，其将所有暴露的硅侧壁与直接下面的导体分开。

公开(公告)号：US4723155A

公开(公告)日：1988-02-02

申请号：US910850

申请日：1986-09-24

Applicant: Yukimasa Uchida

Inventor： Yukimasa Uchida

IPC: H01L23/525 ,  H01L29/06 ,  H01L23/48

CPC classification number: H01L23/5252 ,  H01L23/525 ,  H01L23/5254 ,  H01L23/5256 ,  H01L23/5258 ,  H01L29/0638 ,  H01L2924/0002 ,  Y10S257/926

Abstract: A fuse element is formed on a field insulation film on a semiconductor substrate of n conductivity type in which MOS transistors are formed. A first guard ring region of second conductivity type is provided in the substrate, surrounding the semiconductor substrate region under the fuse element. A second guard ring region of first conductivity type is formed in the substrate, surrounding the first guard ring region. Proper potentials are applied to the first and second guard ring regions.

Abstract translation: 在形成MOS晶体管的n导电型半导体衬底上的场绝缘膜上形成熔丝元件。 第二导电类型的第一保护环区域设置在衬底中，围绕熔丝元件下方的半导体衬底区域。 第一导电类型的第二保护环区域形成在衬底中，围绕第一保护环区域。 适当的电位施加到第一和第二保护环区域。

公开(公告)号：US4699465A

公开(公告)日：1987-10-13

申请号：US829422

申请日：1986-02-13

Applicant: Robert R. Rice ,  Jeffrey R. Heidel

Inventor： Robert R. Rice ,  Jeffrey R. Heidel

IPC: H01S3/00 ,  H01S5/00 ,  H01S5/40 ,  G02B5/18 ,  H01L27/10

CPC classification number: H01S5/4031 ,  H01S3/005 ,  H01S5/005 ,  Y10S257/926

Abstract: A laser diode array produces one set of beams that are out of phase with those of another set of beams, with the beams of one set alternating with those of the other. The phase plate has first and second sets of regions, with the regions of one set alternating with those of the other. The phase plate is positioned in the near field of the beam pattern such that one set of beams passes through one set of regions and the other set of beams passes through the other set of regions. One set of regions changes the phase of the beams passing therethrough to create a substantially single lobed beam pattern in the far field.

Abstract translation: 激光二极管阵列产生与另一组光束不同相的一组光束，其中一组光束与另一组光束交替。 相位板具有第一和第二组区域，其中一组区域与另一组区域交替。 相位板位于波束图案的近场中，使得一组光束穿过一组区域，另一组光束穿过另一组区域。 一组区域改变穿过其中的光束的相位，以在远场中产生基本上单个的叶状波束图案。