公开(公告)号：US20090010054A1

公开(公告)日：2009-01-08

申请号：US11967531

申请日：2007-12-31

申请人： Hee Bok KANG ,  Jin Hong An ,  Suk Kyoung Hong

发明人： Hee Bok KANG ,  Jin Hong An ,  Suk Kyoung Hong

IPC分类号： G11C11/40 ,  G11C7/14 ,  G11C7/06

CPC分类号： G11C7/14 ,  G11C11/22

摘要： A semiconductor memory device includes a one-transistor (1-T) field effect transistor (FET) type memory cell connected between a pair of bit lines, and controlled by a word line, where a different channel resistance is induced to a channel region depending on a polarity state of a ferroelectric layer. The device comprises a plurality of word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a pair of clamp dummy lines arranged in the column direction, a pair of reference dummy lines arranged in the column direction, a cell array including the memory cell and formed in a region where the word line and the bit line are crossed, a dummy cell array including the memory cell and formed where the word line, the pair of claim dummy lines and the pair of reference dummy lines are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage.

摘要翻译： 半导体存储器件包括连接在一对位线之间并由字线控制的单晶体管（1-T）场效应晶体管（FET）型存储单元，其中不同的沟道电阻被引导到通道区域依赖 在铁电层的极性状态。 该装置包括沿行方向排列的多个字线，沿列方向配置的多个位线，沿列方向排列的一对钳位虚拟线，沿列方向配置的一对基准虚拟线， 包括存储单元并形成在字线和位线交叉的区域中的单元阵列，包括存储单元的虚拟单元阵列，并形成在字线，一对声线虚拟线和一对参考虚线之间 以及连接到位线并被配置为接收钳位电压和参考电压的读出放大器和写入驱动单元。