利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

80 条记录 (耗时 0.027 秒)

    Semiconductor memory device removing parasitic coupling capacitance between word lines
    2.
    发明授权
    Semiconductor memory device removing parasitic coupling capacitance between word lines 有权
    半导体存储器件去除字线之间的寄生耦合电容

    公开(公告)号：US08416638B2

    公开(公告)日：2013-04-09

    申请号：US12164216

    申请日：2008-06-30

    申请人： Dong Hwee Kim ,  Jin Hong An

    发明人： Dong Hwee Kim ,  Jin Hong An

    IPC分类号： G11C8/08

    CPC分类号： G11C8/08 ,  G11C8/14

    摘要： A semiconductor memory device includes a main word line shared by a plurality of mats. Each of the mats includes a plurality of sub word lines. A decoding unit is configured to decode a row address bit and output a word line driving signal. A plurality of sub word line driving units are each configured to activate one of the sub word lines according to the word line driving signal. In the semiconductor memory device each neighboring sub word line driving units is connected to a different main word line to remove parasitic coupling capacitance.

    摘要翻译： 半导体存储器件包括由多个垫共享的主字线。 每个垫包括多个子字线。 解码单元被配置为对行地址位进行解码并输出字线驱动信号。 多个子字线驱动单元被配置为根据字线驱动信号激活子字线中的一个。 在半导体存储器件中，每个相邻的子字线驱动单元连接到不同的主字线以去除寄生耦合电容。

    SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF 有权
    半导体存储器件及其驱动方法

    公开(公告)号：US20120314525A1

    公开(公告)日：2012-12-13

    申请号：US13564842

    申请日：2012-08-02

    申请人： Myoung-Jin LEE ,  Jin-Hong AN

    发明人： Myoung-Jin LEE ,  Jin-Hong AN

    IPC分类号： G11C8/08 ,  G11C8/00

    CPC分类号： G11C8/08 ,  G11C11/4076 ,  G11C11/4085

    摘要： A semiconductor memory device includes a plurality of wordlines and a driver configured to, when an wordline of the plurality of wordlines is activated by an active command, drive at least one non-activated wordline neighboring the activated wordline and remaining non-activated wordlines with different wordline driving voltage levels during a period of time that the activated wordline is driven to a high voltage level.

    摘要翻译： 半导体存储器件包括多个字线和驱动器，其被配置为当多个字线的字线被激活命令激活时，驱动与激活的字线相邻的至少一个非激活字线和具有不同的剩余非激活字线 在激活的字线被驱动到高电压电平的时间段内的字线驱动电压电平。

    BATTERY PACK
    5.
    发明申请
    BATTERY PACK 审中-公开
    电池组

    公开(公告)号：US20120121937A1

    公开(公告)日：2012-05-17

    申请号：US13078213

    申请日：2011-04-01

    申请人： Eun-Ok Kwak ,  Jeong-Deok Byun ,  Kyung-Won Seo ,  Jin-Hong An

    发明人： Eun-Ok Kwak ,  Jeong-Deok Byun ,  Kyung-Won Seo ,  Jin-Hong An

    IPC分类号： H01M10/42

    CPC分类号： H01M10/42 ,  H01M2/34

    摘要： A battery pack is constructed with a plurality of bare cells having first and second electrodes, a protection circuit module having at least one through-holes, a first electrode lead electrically connecting the first electrodes and a second electrode lead electrically connecting the second electrodes, and a holder case having supports that support the bare cells. One end of each first and second electrode leads passes through the through-hole of the protection circuit module. The first and second electrode leads electrically connect the bare cells and balance the bare cells by transmitting at least one of voltage and current of the bare cells to the protection circuit module.

    摘要翻译： 电池组由具有第一和第二电极的多个裸电池构成，具有至少一个通孔的保护电路模块，电连接第一电极的第一电极引线和电连接第二电极的第二电极引线，以及 具有支撑裸电池的支架的支架壳体。 每个第一和第二电极引线的一端通过保护电路模块的通孔。 第一和第二电极引线通过将裸电池的电压和电流中的至少一个传输到保护电路模块来电连接裸电池并平衡裸电池。

    Connecting structure of battery stacks
    6.
    发明申请
    Connecting structure of battery stacks 审中-公开
    电池组的连接结构

    公开(公告)号：US20110305936A1

    公开(公告)日：2011-12-15

    申请号：US12929099

    申请日：2010-12-30

    申请人： No-Hyun Kwag ,  Jeong-Deok Byun ,  Jung-Yeop Han ,  Kyung-Won Seo ,  Watson Doh ,  Jin-Hong An

    发明人： No-Hyun Kwag ,  Jeong-Deok Byun ,  Jung-Yeop Han ,  Kyung-Won Seo ,  Watson Doh ,  Jin-Hong An

    IPC分类号： H01M2/20 ,  H01R25/00

    CPC分类号： H01M2/206 ,  H01M2/30 ,  H01M2/32

    摘要： A connecting structure of battery stacks includes an electricity collecting case with a plurality of battery stacks, each battery stack having a plurality of unit battery cells and power terminal portions, at least one bus bar with a plurality of fastening holes along a length direction thereof, the bus bar connecting the battery stacks via respective power terminal portions in the fastening holes, and an insulating layer on a surface of the bus bar.

    摘要翻译： 电池堆的连接结构包括具有多个电池堆的集电箱，每个电池堆具有多个单元电池单元和电源端子部分，至少一个母线沿其长度方向具有多个紧固孔， 通过紧固孔中的相应的电源端子部分连接电池组的母线以及母线表面上的绝缘层。

    Fuel tank and cap device thereof
    7.
    发明授权
    Fuel tank and cap device thereof 有权
    燃油箱及其盖装置

    公开(公告)号：US07971606B2

    公开(公告)日：2011-07-05

    申请号：US11373363

    申请日：2006-03-09

    申请人： Eun Suk Cho ,  Jun Won Suh ,  Jong Ki Lee ,  Ri A Ju ,  Won Hyouk Jang ,  Dong Yun Lee ,  Sang Hyeon Choi ,  Jin Hong An

    发明人： Eun Suk Cho ,  Jun Won Suh ,  Jong Ki Lee ,  Ri A Ju ,  Won Hyouk Jang ,  Dong Yun Lee ,  Sang Hyeon Choi ,  Jin Hong An

    IPC分类号： F16K24/00 ,  F16K24/04 ,  F16L37/44

    CPC分类号： H01M8/04208 ,  Y10T137/86252 ,  Y10T137/86332

    摘要： A fuel tank and a cap device for the fuel tank. The fuel tank is connected to a fuel cell and includes a tank body having a fuel opening and a pin hole for maintaining an inside pressure, a floater positioned on a surface of the fuel stored in the tank body, and an air pipe connected to the pin hole and an upper part of the floater. The cap device includes a cap body having an inside transfer path for connecting an inlet opening for introducing the fuel and an outside transfer pipe, a fixed outer cap including a connector for fixing a discharge opening into which the transfer pipe is inserted, and an elastic opening/closing section in which the cap body is elastically compressible by the connector, and wherein the inside transfer path opens during the compression.

    摘要翻译： 用于燃料箱的燃料箱和盖装置。 燃料箱连接到燃料电池，并且包括具有用于保持内部压力的燃料开口和销孔的罐体，位于储存在罐体中的燃料的表面上的浮子和连接到罐体的空气管 针孔和浮子的上部。 盖装置包括盖主体，其具有内部传送路径，用于连接用于引入燃料的入口和外部输送管;固定外盖，包括用于固定插入有输送管的排出口的连接器，弹性 打开/关闭部分，其中帽体由连接器弹性压缩，并且其中内部传送路径在压缩期间打开。

    BATTERY PACK
    8.
    发明申请
    BATTERY PACK 有权
    电池组

    公开(公告)号：US20110135993A1

    公开(公告)日：2011-06-09

    申请号：US12768103

    申请日：2010-04-27

    申请人： Jin-Hong AN ,  No-Hyun Kwag

    发明人： Jin-Hong AN ,  No-Hyun Kwag

    IPC分类号： H01M6/42

    CPC分类号： H01M2/1077 ,  H01M6/44 ,  H01M10/613 ,  H01M10/643 ,  H01M10/6551 ,  H01M10/6557

    摘要： A battery pack including a plurality of battery cells and having improved battery lifetime. The battery pack includes a holder case defining a plurality of cell spaces; and a plurality of battery cells are accommodated in a pattern in a portion of the plurality of cell spaces, wherein some of the plurality of cell spaces are empty.

    摘要翻译： 一种包括多个电池单元并且具有改善的电池寿命的电池组。 电池组包括限定多个电池空间的保持器壳体; 并且多个电池单元容纳在多个单元空间的一部分中的图案中，其中多个单元空间中的一些是空的。

    Semiconductor memory device with ferroelectric device
    9.
    发明授权
    Semiconductor memory device with ferroelectric device 失效
    具有铁电元件的半导体存储器件

    公开(公告)号：US07668031B2

    公开(公告)日：2010-02-23

    申请号：US11967531

    申请日：2007-12-31

    申请人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

    发明人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

    IPC分类号： G11C7/02

    CPC分类号： G11C7/14 ,  G11C11/22

    摘要： A semiconductor memory device includes a one-transistor (1-T) field effect transistor (FET) type memory cell connected between a pair of bit lines, and controlled by a word line, where a different channel resistance is induced to a channel region depending on a polarity state of a ferroelectric layer. The device includes a plurality of word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a pair of clamp dummy lines arranged in the column direction, a pair of reference dummy lines arranged in the column direction, a cell array including the memory cell and formed in a region where the word line and the bit line are crossed, a dummy cell array including the memory cell and formed where the word line, the pair of claim dummy lines and the pair of reference dummy lines are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage.

    摘要翻译： 半导体存储器件包括连接在一对位线之间并由字线控制的单晶体管（1-T）场效应晶体管（FET）型存储单元，其中不同的沟道电阻被引导到通道区域依赖 在铁电层的极性状态。 该装置包括排列成行方向的多个字线，沿列方向配置的多个位线，沿列方向排列的一对钳位虚拟线，沿列方向排列的一对基准虚拟线， 包括存储单元并形成在字线和位线交叉的区域中的单元阵列，包括存储单元的虚拟单元阵列，并形成在字线，一对声线虚拟线和一对参考虚线之间 以及连接到位线并被配置为接收钳位电压和参考电压的读出放大器和写入驱动单元。

    Phase change memory device
    10.
    发明授权
    Phase change memory device 有权
    相变存储器件

    公开(公告)号：US07663910B2

    公开(公告)日：2010-02-16

    申请号：US12135241

    申请日：2008-06-09

    申请人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

    发明人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0038 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/72

    摘要： A phase change memory device includes a plurality of word lines arranged in a row direction and a plurality of bit lines arranged in a column direction. A plurality of reference bit line and a plurality of clamp bit lines are arranged in the column direction. A cell array block including a phase change resistance cell is arranged where a word line and a bit line intersect. A reference cell array block is formed where a word line and the reference bit line intersect. The reference cell array block is configured to output a reference current. A clamp cell array block is formed where a word line and a clamp bit line intersect. The clamp cell array block is configured to output a clamp current. A sense amplifier is connected to each of the bit lines and is configured to receive a clamp voltage and a reference voltage.

    摘要翻译： 相变存储器件包括沿行方向布置的多个字线和沿列方向布置的多个位线。 多个基准位线和多个钳位位线在列方向上排列。 布置包括相变电阻单元的单元阵列块，其中字线和位线相交。 形成参考单元阵列块，其中字线和参考位线相交。 参考单元阵列块被配置为输出参考电流。 形成钳位单元阵列块，其中字线和钳位位线相交。 钳位单元阵列块被配置为输出钳位电流。 感测放大器连接到每个位线，并且被配置为接收钳位电压和参考电压。