公开(公告)号：US5606731A

公开(公告)日：1997-02-25

申请号：US399805

申请日：1995-03-07

Applicant: Gary L. Pace ,  Vance H. Peterson ,  Edgar H. Callaway, Jr.

Inventor： Gary L. Pace ,  Vance H. Peterson ,  Edgar H. Callaway, Jr.

IPC: H03D3/24 ,  H03J7/04 ,  H04B1/30

CPC classification number: H03D3/242 ,  H03J7/04 ,  H04B1/30

Abstract: A zero-intermediate frequency receiver circuit (11) for receiving a radio frequency signal detected by an antenna (14). The receiver circuit (10) comprises a second local oscillator circuit (25) and an oscillator circuit (60) of a phase locked loop demodulator (36) which are identical and track each other so as to provide a more accurate reference for processing a demodulated signal. A current reference (39) providing a current reference signal utilized by the second local oscillator circuit (25) and the oscillator circuit (60) of the phase locked loop demodulator (36).

Abstract translation: 一种用于接收由天线（14）检测的射频信号的零中频接收机电路（11）。 接收机电路（10）包括第二本地振荡器电路（25）和锁相环解调器（36）的振荡器电路（60），它们彼此相同并相互跟踪，以便提供更准确的参考用于处理解调的 信号。 提供由第二本地振荡器电路（25）和锁相环解调器（36）的振荡器电路（60）使用的电流参考信号的电流参考（39）。

公开(公告)号：US5604926A

公开(公告)日：1997-02-18

申请号：US399784

申请日：1995-03-07

Applicant: Gary L. Pace ,  Vance H. Peterson ,  Edgar H. Callaway, Jr.

Inventor： Gary L. Pace ,  Vance H. Peterson ,  Edgar H. Callaway, Jr.

IPC: H03D3/24 ,  H03D13/00 ,  H03L7/085 ,  H03L7/093 ,  H03L7/183 ,  H04B1/26 ,  H04B1/30

CPC classification number: H03L7/085 ,  H03D3/241 ,  H03L7/093 ,  H03L7/183 ,  H04B1/26 ,  H03D13/00

Abstract: A phase locked loop (PLL) circuit for use as a demodulator and other applications. The PLL circuit (200) comprises a phase detector (210), a transconductance amplifier (212) and a current controlled oscillator (ICO) (214). The phase detector has two signal inputs and two outputs, and detects a phase difference between signals at its inputs. A capacitor C1 is connected to the output of phase detector (210) and develops an output voltage signal vo(t). A transconductance amplifier (212) is coupled to the capacitor C1 and converts the output voltage signal vo(t) to an output current signal. The ICO (214) is coupled to the transconductance amplifier (212) and the second output of the phase detector (210) and generates an output signal having a frequency which is proportional to an input current signal. The output signal of the ICO (214) is coupled to the second signal input of the phase detector (212).

Abstract translation: 用作解调器和其他应用的锁相环（PLL）电路。 PLL电路（200）包括相位检测器（210），跨导放大器（212）和电流控制振荡器（ICO）（214）。 相位检测器具有两个信号输入和两个输出，并检测其输入信号之间的相位差。 电容器C1连接到相位检测器（210）的输出端并产生输出电压信号vo（t）。 跨导放大器（212）耦合到电容器C1，并将输出电压信号vo（t）转换成输出电流信号。 ICO（214）耦合到跨导放大器（212）和相位检测器（210）的第二输出端，并产生具有与输入电流信号成比例的频率的输出信号。 ICO（214）的输出信号耦合到相位检测器（212）的第二信号输入端。

公开(公告)号：US5063357A

公开(公告)日：1991-11-05

申请号：US562361

申请日：1990-08-03

Applicant: William R. Williams ,  Edgar H. Callaway, Jr.

Inventor： William R. Williams ,  Edgar H. Callaway, Jr.

IPC: H03L7/07

CPC classification number: H03L7/07

Abstract: A high stability oscillator circuit 100 having an output 150 and a multiple of reference oscillators 102, 104, and 106 for enhanced stability and reliability is disclosed. The output signals of these oscillators 108, 110, and 112 are mixed and analyzed for determination of excessive frequency shift including component failure. Additionally a switch 148 decouples the shifted oscillator signal from the output of the circuit 150 and couples another one of the oscillators in its place.

Abstract translation: 公开了一种具有输出150和多个参考振荡器102,104和106的高稳定性振荡器电路100，用于增强稳定性和可靠性。 对这些振荡器108,110和112的输出信号进行混合和分析，以确定包括组件故障在内的过大的频移。 此外，开关148将移位的振荡器信号与电路150的输出分离，并将另一个振荡器耦合到其位置。