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    CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE
    1.
    发明公开
    CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240242753A1

    公开(公告)日：2024-07-18

    申请号：US18510829

    申请日：2023-11-16

    Applicant: Winbond Electronics Corp

    Inventor： Shinya OKUNO

    IPC: G11C11/4076 ,  G11C11/4093 ,  H03L7/183

    CPC classification number: G11C11/4076 ,  G11C11/4093 ,  H03L7/183

    Abstract: A control circuit is provided herein, which can suppress the prolongation of a delay operation, so that the sequence using the DLL circuit to adjust the delay of the internal clock signal can be finished within a predetermined execution period. A control circuit includes a delay control unit delaying an input clock signal to generate an output clock signal based on the phase difference between the input clock signal and an output clock signal. The control circuit further includes a clock control unit. When the phase difference is greater than the first predetermined amount, the clock control unit inputs a clock signal delayed from the input clock signal by a second predetermined amount to the delay control unit as the input clock signal.

    Time-to-digital converter circuitry
    2.
    发明授权
    Time-to-digital converter circuitry 有权

    公开(公告)号：US12032340B2

    公开(公告)日：2024-07-09

    申请号：US18236222

    申请日：2023-08-21

    Applicant: Telefonaktiebolaget LM Ericsson (publ)

    Inventor： Mohammed Abdulaziz ,  Henrik Sjöland ,  Tony Påhlsson

    IPC: G04F10/00 ,  H03L7/081 ,  H03L7/183

    CPC classification number: G04F10/005 ,  H03L7/0818 ,  H03L7/183

    Abstract: A time-to-digital converter (TDC) circuitry for converting a phase difference between an input reference signal and an input clock signal to a digitally represented output signal. The TDC circuitry comprises multiple constituent TDCs, a reference signal provider, and a digital signal combiner. Each TDC is configured to convert a phase difference between a constituent reference signal and a constituent clock signal to a digitally represented constituent output signal. The reference signal provider is configured to provide the respective constituent reference signals to each of the TDCs. In at least a parallel operation mode of the TDC circuitry, each respective constituent reference signal comprises a respectively delayed version of the input reference signal with different respective delays for at least two of the respective constituent reference signals. The digital signal combiner is configured to provide the digitally represented output signal based on the digitally represented constituent output signals of the TDCs.

    SYSTEMS HAVING A PHASE FREQUENCY DETECTOR
    3.
    发明公开
    SYSTEMS HAVING A PHASE FREQUENCY DETECTOR 审中-公开

    公开(公告)号：US20240187003A1

    公开(公告)日：2024-06-06

    申请号：US18284805

    申请日：2021-05-06

    Applicant: Micron Technology, Inc.

    Inventor： Junjun Wang

    IPC: H03L7/089 ,  H03L7/099 ,  H03L7/183

    CPC classification number: H03L7/089 ,  H03L7/0991 ,  H03L7/183

    Abstract: A variety of applications can include a phase frequency detector structured to track the falling edges of two input signals to detect a phase difference between the two signals and to generate one or more signals that can be used to adjust one of the signals with respect to the other when the phase difference is greater than 180 degrees. The phase frequency detector can be implemented in a phase lock loop circuit to track the falling edges of a reference clock signal and the falling edge of a feedback signal. In response to detection of the phase difference between the reference clock signal and the feedback signal being greater than 180 degrees using the falling edges of these signals, the phase frequency detector can adjust its output signals to provide for recovery of a lock condition for the reference clock signal. Additional devices, systems, and methods are discussed.

    DELAY LOCKED LOOP AND MEMORY
    4.
    发明公开
    DELAY LOCKED LOOP AND MEMORY 审中-公开

    公开(公告)号：US20240063802A1

    公开(公告)日：2024-02-22

    申请号：US18448946

    申请日：2023-08-13

    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

    Inventor： Siman LI ,  YOONJOO EOM

    IPC: H03L7/087 ,  H03L7/183 ,  H03K19/21

    CPC classification number: H03L7/087 ,  H03L7/183 ,  H03K19/21

    Abstract: A delay locked loop includes a preprocessing module, a first regulable delay line, a second regulable delay line and a first regulation module. The preprocessing module is configured to receive an initial clock signal, preprocess the initial clock signal, and output a first clock signal and a second clock signal. The first regulable delay line is configured to receive the first clock signal, regulate and transmit the first clock signal, and output a first target clock signal. The second regulable delay line is configured to receive the second clock signal, regulate and transmit the second clock signal, and output a second synchronization clock signal. The first regulation module is configured to regulate delay of the second synchronization clock signal based on the first target clock signal, and output a second target clock signal.

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