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公开(公告)号：US20140019714A1
公开(公告)日：2014-01-16
申请号：US13993068
申请日：2011-12-30
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30025 , G06F9/30036 , H03M7/46 , H03M7/6005
摘要： A processor core that includes a hardware decode unit and an execution engine unit. The hardware decode unit to decode a vector frequency expand instruction, wherein the vector frequency compress instruction includes a source operand and a destination operand, wherein the source operand specifies a source vector register that includes one or more pairs of a value and run length that are to be expanded into a run of that value based on the run length. The execution engine unit to execute the decoded vector frequency expand instruction which causes, a set of one or more source data elements in the source vector register to be expanded into a set of destination data elements comprising more elements than the set of source data elements and including at least one run of identical values which were run length encoded in the source vector register.
摘要翻译： 包括硬件解码单元和执行引擎单元的处理器核心。 所述硬件解码单元对矢量频率扩展指令进行解码，其中所述向量频率压缩指令包括源操作数和目的操作数，其中所述源操作数指定源向量寄存器，所述源向量寄存器包括一对或多对值和游程长度， 根据运行长度将其扩展为该值的运行。 执行引擎单元，用于执行解码矢量频率扩展指令，其使得源向量寄存器中的一个或多个源数据元素的集合被扩展为包括比该源数据元素集合更多的元素的一组目的地数据元素，以及 包括在源向量寄存器中运行长度编码的至少一个相同值的运行。
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32.发明申请VECTOR INSTRUCTION FOR PRESENTING COMPLEX CONJUGATES OF RESPECTIVE COMPLEX NUMBERS 有权提出相关复合编号复合函数的向量指令公开(公告)号：US20130275731A1
公开(公告)日：2013-10-17
申请号：US13977614
申请日：2011-12-22
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30036 , G06F17/5022
摘要： An apparatus is described having a semiconductor chip that has an instruction execution pipeline. The instruction execution pipeline has an execution unit with logic circuitry to perform the following for an instruction: accept input vector elements representing real and imaginary parts of a plurality of complex numbers; and, present the complex conjugates of the complex numbers.
摘要翻译： 描述具有具有指令执行流水线的半导体芯片的装置。 指令执行流水线具有执行单元，其具有用于对指令执行以下操作的逻辑电路：接受表示多个复数的实部和虚部的输入向量元素; 并且呈现复数的复共轭。
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