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    TECHNOLOGIES FOR NETWORK PATH AND TOPOLOGY MANAGEMENT
    2.
    发明申请
    TECHNOLOGIES FOR NETWORK PATH AND TOPOLOGY MANAGEMENT 有权

    公开(公告)号：US20220124548A1

    公开(公告)日：2022-04-21

    申请号：US17561225

    申请日：2021-12-23

    申请人： Amar Srivastava ,  Kshitij A. Doshi ,  Cristian Florin Dumitrescu ,  Christian Maciocco

    发明人： Amar Srivastava ,  Kshitij A. Doshi ,  Cristian Florin Dumitrescu ,  Christian Maciocco

    IPC分类号： H04W28/02 ,  H04W40/24 ,  H04W28/10 ,  H04L5/14

    摘要： The present disclosure relates to techniques for determining optimal routing paths for computing devices in a network, including selecting an optimal gateway among a number of available gateways. The techniques include gathering data regarding characteristics of a network, including gateways and network access nodes (NANs) in at least one access network. The characteristics can include, e.g., supported frequency bands, communication protocols, signal-to-noise ratio, power, signal noise and quality, slicing information, and whether a network vender is a standalone network vendor or a non-standalone network vendor. In one aspect, the characteristics are obtained using the Mobile Broadband Interface Model (MBIM). The characteristics can be used by devices in determining routing paths based on requirements of individual flows and/or workflows of individual application instances.

    Vector frequency expand instruction
    3.
    发明授权
    Vector frequency expand instruction 有权

    公开(公告)号：US10241792B2

    公开(公告)日：2019-03-26

    申请号：US13993068

    申请日：2011-12-30

    申请人： Elmoustapha Ould-Ahmed-Vall ,  Suleyman Sair ,  Kshitij A. Doshi ,  Charles Yount ,  Bret L. Toll

    发明人： Elmoustapha Ould-Ahmed-Vall ,  Suleyman Sair ,  Kshitij A. Doshi ,  Charles Yount ,  Bret L. Toll

    IPC分类号： G06F9/30 ,  H03M7/46 ,  H03M7/30

    摘要： A processor core that includes a hardware decode unit and an execution engine unit. The hardware decode unit to decode a vector frequency expand instruction, wherein the vector frequency compress instruction includes a source operand and a destination operand, wherein the source operand specifies a source vector register that includes one or more pairs of a value and run length that are to be expanded into a run of that value based on the run length. The execution engine unit to execute the decoded vector frequency expand instruction which causes, a set of one or more source data elements in the source vector register to be expanded into a set of destination data elements comprising more elements than the set of source data elements and including at least one run of identical values which were run length encoded in the source vector register.

    APPARATUS AND METHOD FOR LOW-OVERHEAD SYNCHRONOUS PAGE TABLE UPDATES
    6.
    发明申请
    APPARATUS AND METHOD FOR LOW-OVERHEAD SYNCHRONOUS PAGE TABLE UPDATES 审中-公开

    公开(公告)号：US20170286300A1

    公开(公告)日：2017-10-05

    申请号：US15088985

    申请日：2016-04-01

    申请人： KSHITIJ A. DOSHI ,  CHRISTOPHER J. HUGHES

    发明人： KSHITIJ A. DOSHI ,  CHRISTOPHER J. HUGHES

    IPC分类号： G06F12/08 ,  G06F12/10

    CPC分类号： G06F12/0831 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/621 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/682

    摘要： An apparatus and method are described for low overhead synchronous page table updates. For example, one embodiment of a processor comprises: a set of one or more cores to execute instructions and process data; a translation lookaside buffer (TLB) comprising a plurality of entries to cache virtual-to-physical address translations usable by the set of one or more cores when executing the instructions; locking circuitry to allow a thread to lock a first page table entry (PTE) in the TLB to ensure that only one thread can modify the first PTE at a time, wherein the TLB is to modify the first PTE upon the thread acquiring the lock; a PTE invalidation circuit to execute a PTE invalidate instruction on a first core to invalidate the first PTE in other TLBs of other cores, the PTE invalidation circuit, responsive to execution of the PTE invalidate instruction, to responsively determine a number of other TLBs of other cores which need to be notified of the PTE invalidation, transmit PTE invalidate messages to the other TLBs, and wait for responses; and the locking circuitry to release the lock on the first PTE responsive to receiving responses from all of the other TLBs.

    VECTOR FREQUENCY COMPRESS INSTRUCTION
    8.
    发明申请
    VECTOR FREQUENCY COMPRESS INSTRUCTION 有权
    矢量频率压缩指令

    公开(公告)号：US20140317377A1

    公开(公告)日：2014-10-23

    申请号：US13993058

    申请日：2011-12-30

    申请人： Elmoustapha Ould-Ahmed-Vall ,  Suleyman Sair ,  Kshitij A. Doshi ,  Charles R. Yount ,  Bret L. Toll

    发明人： Elmoustapha Ould-Ahmed-Vall ,  Suleyman Sair ,  Kshitij A. Doshi ,  Charles R. Yount ,  Bret L. Toll

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30036 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/3016 ,  H03M7/46 ,  H03M7/6005

    摘要： A processor core that includes a hardware decode unit to decode a vector frequency compress instruction that includes a source operand and a destination operand. The source operand specifying a source vector register that includes a plurality of source data elements including one or more runs of identical data elements that are each to be compressed in a destination vector register as a value and run length pair. The destination operand identifies the destination vector register. The processor core also includes an execution engine unit to execute the decoded vector frequency compress instruction which causes, for each source data element, a value to be copied into the destination vector register to indicate that source data element's value. One or more runs of the source data elements equal are encoded in the destination vector register as the predetermined compression value followed by a run length for that run.

    摘要翻译： 一种处理器核心，其包括用于解码包括源操作数和目的地操作数的向量频率压缩指令的硬件解码单元。 源操作数指定源向量寄存器，其包括多个源数据元素，其包括在目的地向量寄存器中各自被压缩的相同数据元素的一个或多个游程作为值和游程长度对。 目标操作数标识目标向量寄存器。 处理器核心还包括执行引擎单元，用于执行解码的向量频率压缩指令，其对于每个源数据元素，其将被复制到目的地向量寄存器中的值指示源数据元素的值。 源数据元素相等的一个或多个运行在目标向量寄存器中被编码为预定压缩值，后跟该运行的运行长度。

    INSTRUCTION AND LOGIC TO PROVIDE VECTOR HORIZONTAL COMPARE FUNCTIONALITY
    10.
    发明申请
    INSTRUCTION AND LOGIC TO PROVIDE VECTOR HORIZONTAL COMPARE FUNCTIONALITY 有权
    指令和逻辑提供矢量水平比较功能

    公开(公告)号：US20140258683A1

    公开(公告)日：2014-09-11

    申请号：US13977733

    申请日：2011-11-30

    申请人： Elmoustapha Ould-Ahmed-Vall ,  Charles R. Yount ,  Suleyman Sair ,  Kshitij A. Doshi

    发明人： Elmoustapha Ould-Ahmed-Vall ,  Charles R. Yount ,  Suleyman Sair ,  Kshitij A. Doshi

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30145 ,  G06F7/02 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30036

    摘要： Instructions and logic provide vector horizontal compare functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read values from data fields of the specified size in the source operand, corresponding to the mask and compare the values for equality. In some embodiments, responsive to a detection of inequality, a trap may be taken. In some alternative embodiments, a flag may be set. In other alternative embodiments, a mask field may be set to a masked state for the corresponding unequal value(s). In some embodiments, responsive to all unmasked data fields of the source operand being equal to a particular value, that value may be broadcast to all data fields of the specified size in the destination operand.

    摘要翻译： 指令和逻辑提供向量横向比较功能。 一些实施例，响应于指定目的地操作数，向量元素的大小，源操作数和对应于源操作数中的向量元素数据字段的一部分的掩码的指令; 从源操作数中的指定大小的数据字段读取值，对应于掩码，并比较相等的值。 在一些实施例中，响应于不等式的检测，可以采取陷阱。 在一些替代实施例中，可以设置标志。 在其他替代实施例中，可以将掩模字段设置为对应不等值的掩蔽状态。 在一些实施例中，响应于源操作数的所有未屏蔽的数据字段等于特定值，该值可以广播到目的地操作数中指定大小的所有数据字段。