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58 条记录 (耗时 0.03 秒)

    Slack sensitivity to parameter variation based timing analysis
    33.
    发明授权
    Slack sensitivity to parameter variation based timing analysis 有权
    对基于参数变化的时序分析的松弛敏感性

    公开(公告)号：US07401307B2

    公开(公告)日：2008-07-15

    申请号：US10904309

    申请日：2004-11-03

    申请人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Jeffrey H. Oppold ,  Anthony D. Polson

    发明人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Jeffrey H. Oppold ,  Anthony D. Polson

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F17/5045

    摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.

    摘要翻译： 公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。 通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。 对于每个独立参数重复此步骤。 然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。 然后将失败的定时终点根据其故障系数进行优先级修改。 所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。

    Method and system for evaluating timing in an integrated circuit
    34.
    发明授权
    Method and system for evaluating timing in an integrated circuit 有权
    用于评估集成电路中的定时的方法和系统

    公开(公告)号：US07962874B2

    公开(公告)日：2011-06-14

    申请号：US12183549

    申请日：2008-07-31

    申请人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

    发明人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

    IPC分类号： G06F17/50

    CPC分类号： G01R31/3016

    摘要： Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.

    摘要翻译： 用于分析集成电路中的定时并减少静态时序分析（STA）中定时松弛计算中的悲观情况的方法。 该方法涉及分组和消除在早期和晚期电路路径中具有类似延迟的元件的延迟贡献。 使用具有不同延迟的元件的延迟贡献来计算调整的定时松弛。 在一些实施例中，具有不同延迟的元件的延迟贡献是根和平方。 本发明的实施例提供了用于减少由于基于单元和线依赖的延迟引起的悲观的方法。 在本发明的实施例中考虑的延迟可以包括由于路径中的元件的位置而导致的延迟。

    Method and system for evaluating timing in an integrated circuit
    36.
    发明授权
    Method and system for evaluating timing in an integrated circuit 失效
    用于评估集成电路中的定时的方法和系统

    公开(公告)号：US07089143B2

    公开(公告)日：2006-08-08

    申请号：US10709361

    申请日：2004-04-29

    申请人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

    发明人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

    IPC分类号： G01M19/00 ,  G06F9/45

    CPC分类号： G01R31/3016

    摘要： Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.

    摘要翻译： 用于分析集成电路中的定时并减少静态时序分析（STA）中定时松弛计算中的悲观情况的方法。 该方法涉及分组和消除在早期和晚期电路路径中具有类似延迟的元件的延迟贡献。 使用具有不同延迟的元件的延迟贡献来计算调整的定时松弛。 在一些实施例中，具有不同延迟的元件的延迟贡献是根和平方。 本发明的实施例提供了用于减少由于基于单元和线依赖的延迟引起的悲观的方法。 在本发明的实施例中考虑的延迟可以包括由于路径中的元件的位置而导致的延迟。

    Methods for identifying failing timing requirements in a digital design
    39.
    发明授权
    Methods for identifying failing timing requirements in a digital design 有权
    识别数字设计中的故障定时要求的方法

    公开(公告)号：US07886246B2

    公开(公告)日：2011-02-08

    申请号：US12103845

    申请日：2008-04-16

    申请人： Nathan C. Buck ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Chandramouli Visweswariah

    发明人： Nathan C. Buck ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Chandramouli Visweswariah

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5031

    摘要： Methods for identifying failing timing requirements in a digital design. The method includes identifying at least one timing test in the digital design that has a passing slack in a base process corner and a failing slack in a different process corner. The method further includes computing a sensitivity of the failing slack to each of a plurality of variables and comparing each sensitivity to a respective sensitivity threshold. If the sensitivity of at least one of the variables is greater than the respective sensitivity threshold, then the at least one timing test is considered to fail.

    摘要翻译： 识别数字设计中的故障定时要求的方法。 该方法包括识别数字设计中的至少一个定时测试，其在基本过程角落中具有通过松弛，并且在不同的过程角落中发生故障的松弛。 该方法还包括计算对于多个变量中的每一个的故障松弛的灵敏度，并将每个灵敏度与相应的灵敏度阈值进行比较。 如果至少一个变量的灵敏度大于相应的灵敏度阈值，则认为至少一个定时测试失败。