公开(公告)号：US20060098503A1

公开(公告)日：2006-05-11

申请号：US11270184

申请日：2005-11-09

申请人： Chang-Yeong Jeong ,  Hong-Sun Hwang

发明人： Chang-Yeong Jeong ,  Hong-Sun Hwang

IPC分类号： G11C29/00

CPC分类号： G11C29/808

摘要： Apparatus and methods are provided for repairing semiconductor memory devices having an open bit line sense amplifier architecture with cell array blocks having memory blocks formed of edge sub-blocks, main sub-blocks, dummy sub-blocks. Row defects can be processed using a straight edge block when DQ data are outputted by enabling three word lines such that a repair process for the memory device in an edge sub-block or a dummy sub-block has the same repair efficiency as that of a case where defects occur in a main sub-block.

摘要翻译： 提供了用于修复具有开放位线读出放大器架构的半导体存储器件的装置和方法，其中单元阵列块具有由边缘子块，主子块，虚拟子块形成的存储块。 当通过使能三个字线输出DQ数据时，可以使用直边块处理行缺陷，使得边缘子块或伪子块中的存储器件的修复处理具有与 在主子块中出现缺陷的情况。

公开(公告)号：US5796668A

公开(公告)日：1998-08-18

申请号：US709622

申请日：1996-09-06

申请人： Dong-Il Seo ,  Hong-Sun Hwang

发明人： Dong-Il Seo ,  Hong-Sun Hwang

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4096 ,  G11C8/00

CPC分类号： G11C7/1015 ,  G11C11/409 ,  G11C11/4096

摘要： An integrated circuit memory device includes a plurality of memory cells arranged in an array of rows and columns, a plurality of word lines wherein each of the word lines is associated with a predetermined row of the memory cells, and a plurality of common lines wherein each of the column lines is associated with a predetermined column of the memory cells. Each of a plurality of sense amplifiers is associated with a respective column line and each of the sense amplifiers detects a voltage difference between a pair of bit lines for the respective column and amplifies the voltage difference. A row decoder selects one of the word lines in response to a row address input during a write operation. An input/output driver receives data input during the write operation, and each of a plurality of input/output gates is connected between the input/output driver and a respective one of the column lines. A column decoder activates one of the input/output gates before the sense amplifier senses and amplifies the voltage difference. Related methods are also disclosed.

摘要翻译： 一种集成电路存储器件，包括排列成行和列阵列的多个存储器单元，多条字线，其中每条字线与存储器单元的预定行相关联，以及多条公共线，其中每条 的列线与存储器单元的预定列相关联。 多个读出放大器中的每一个与相应的列线相关联，并且每个读出放大器检测用于各列的一对位线之间的电压差，并放大电压差。 一行解码器在写入操作期间响应于输入的行地址来选择字线之一。 输入/输出驱动器在写入操作期间接收数据输入，并且多个输入/输出门中的每一个连接在输入/输出驱动器和相应的列线之间。 在读出放大器感测并放大电压差之前，列解码器激活输入/输出门之一。 还公开了相关方法。

公开(公告)号：US5757714A

公开(公告)日：1998-05-26

申请号：US755477

申请日：1996-11-22

申请人： Jong-Hyun Choi ,  Hong-Sun Hwang

发明人： Jong-Hyun Choi ,  Hong-Sun Hwang

IPC分类号： G11C11/413 ,  G05F3/24 ,  G11C5/14 ,  G11C11/407 ,  H01L27/10 ,  G11C7/00

CPC分类号： G11C5/143

摘要： A semiconductor memory device uses three different power supply voltage levels including an internal IVcc, ground Vss and a boosted level Vpp more positive than the internal Vcc. A precharge control circuit in the memory device includes at least one NMOS transistor, at least one PMOS transistor and an output node having voltage values ranging from the IVcc either to Vss or to Vpp. The NMOS transistor acts as a loading transistor to the PMOS transistor and prevents latch-up in the PMOS transistor by maintaining IVcc below Vpp during the initial power set-up period of the memory device.

摘要翻译： 半导体存储器件使用三个不同的电源电压电平，包括内部IVcc，接地Vss和升压电平Vpp比内部Vcc更正。 存储器件中的预充电控制电路包括至少一个NMOS晶体管，至少一个PMOS晶体管和具有范围从IVcc到Vss或Vpp的电压值的输出节点。 NMOS晶体管充当PMOS晶体管的负载晶体管，并通过在存储器件的初始功率建立期间将IVcc保持在Vpp以下，来防止PMOS晶体管中的闩锁。