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公开(公告)号：US12105640B2
公开(公告)日：2024-10-01
申请号：US17945242
申请日：2022-09-15
IPC分类号： G06F12/00 , G06F9/30 , G06F9/54 , G06F11/10 , G06F12/02 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/0817 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F12/128 , G06F13/16 , G06F15/80 , G11C5/06 , G11C7/10 , G11C7/22 , G11C29/42 , G11C29/44
CPC分类号： G06F12/128 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/082 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/1015 , G11C7/106 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/603 , G06F2212/6032 , G06F2212/6042 , G06F2212/608 , G06F2212/62
摘要： Methods, apparatus, systems and articles of manufacture are disclosed to evict in a dual datapath victim cache system. An example apparatus includes a cache storage, a cache controller operable to receive a first memory operation and a second memory operation concurrently, comparison logic operable to identify if the first and second memory operations missed in the cache storage, and a replacement policy component operable to, when at least one of the first and second memory operations corresponds to a miss in the cache storage, reserve an entry in the cache storage to evict based on the first and second memory operations.
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公开(公告)号：US12072814B2
公开(公告)日：2024-08-27
申请号：US18309893
申请日：2023-05-01
IPC分类号： G06F12/128 , G06F9/30 , G06F9/54 , G06F11/10 , G06F12/02 , G06F12/08 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/0817 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F13/16 , G06F15/80 , G11C5/06 , G11C7/10 , G11C7/22 , G11C29/42 , G11C29/44
CPC分类号： G06F12/128 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/082 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/1015 , G11C7/106 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/603 , G06F2212/6032 , G06F2212/6042 , G06F2212/608 , G06F2212/62
摘要： Methods, apparatus, systems and articles of manufacture are disclosed to facilitate read-modify-write support in a victim cache. An example apparatus includes a first storage coupled to a controller, a second storage coupled to the controller and parallel coupled to the first storage, and a storage queue coupled to the first storage, the second storage, and to the controller, the storage queue to obtain a memory operation from the controller indicating an address and a first set of data, obtain a second set of data associated with the address from at least one of the first storage and the second storage, merge the first set of data and the second set of data to produce a third set of data, and provide the third set of data for writing to at least one of the first storage and the second storage.
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公开(公告)号：US20240264952A1
公开(公告)日：2024-08-08
申请号：US18639013
申请日：2024-04-18
IPC分类号： G06F12/128 , G06F9/30 , G06F9/54 , G06F11/10 , G06F12/02 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/0817 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F13/16 , G06F15/80 , G11C5/06 , G11C7/10 , G11C7/22 , G11C29/42 , G11C29/44
CPC分类号： G06F12/128 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/082 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/1015 , G11C7/106 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/603 , G06F2212/6032 , G06F2212/6042 , G06F2212/608 , G06F2212/62
摘要： A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.
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公开(公告)号：US12001345B2
公开(公告)日：2024-06-04
申请号：US18340944
申请日：2023-06-26
IPC分类号： G06F12/12 , G06F9/30 , G06F9/54 , G06F11/10 , G06F12/02 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/0817 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/121 , G06F12/126 , G06F12/127 , G06F12/128 , G06F13/16 , G06F15/80 , G11C5/06 , G11C7/10 , G11C7/22 , G11C29/42 , G11C29/44
CPC分类号： G06F12/128 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/082 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/1015 , G11C7/106 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/6032 , G06F2212/6042 , G06F2212/608 , G06F2212/62
摘要： A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.
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公开(公告)号：US11940929B2
公开(公告)日：2024-03-26
申请号：US16882234
申请日：2020-05-22
IPC分类号： G06F12/0888 , G06F9/30 , G06F9/54 , G06F11/10 , G06F12/02 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/0817 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F12/128 , G06F13/16 , G06F15/80 , G11C5/06 , G11C7/10 , G11C7/22 , G11C29/42 , G11C29/44
CPC分类号： G06F12/128 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/082 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/1015 , G11C7/106 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/6032 , G06F2212/6042 , G06F2212/608 , G06F2212/62
摘要： Methods, apparatus, systems and articles of manufacture are disclosed to reduce read-modify-write cycles for non-aligned writes. An example apparatus includes a memory that includes a plurality of memory banks, an interface configured to be coupled to a central processing unit, the interface to obtain a write operation from the central processing unit, wherein the write operation is to write a subset of the plurality of memory banks, and bank processing logic coupled to the interface and to the memory, the bank processing logic to determine the subset of the plurality of memory banks to write based on the write operation, and determine whether to cause a read operation to be performed in response to the write operation based on whether a number of addresses in the subset of the plurality of memory banks to write satisfies a threshold.
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公开(公告)号：US20230342305A1
公开(公告)日：2023-10-26
申请号：US18340944
申请日：2023-06-26
IPC分类号： G06F12/0804 , G06F12/0884 , G06F12/0888 , G06F9/54 , G06F12/0811 , G11C7/10 , G06F11/10 , G06F12/12 , G06F12/0806 , G06F12/121 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/126 , G06F12/0891 , G06F12/02 , G06F12/128 , G06F12/0817 , G11C29/42 , G11C29/44 , G06F12/0855 , G06F12/0853 , G06F12/0897 , G06F9/30 , G06F12/0815 , G06F13/16 , G06F12/0802
CPC分类号： G06F12/126 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/082 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/128 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/1015 , G11C7/106 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/6032 , G06F2212/6042 , G06F2212/608 , G06F2212/62
摘要： A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.
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公开(公告)号：US11714760B2
公开(公告)日：2023-08-01
申请号：US16882264
申请日：2020-05-22
IPC分类号： G06F12/0811 , G06F9/30 , G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/02 , G06F12/128 , G06F12/0817 , G06F12/0804 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802
CPC分类号： G06F12/0811 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/0802 , G06F12/082 , G06F12/0804 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/128 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/106 , G11C7/1015 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/608 , G06F2212/6032 , G06F2212/62
摘要： Methods, apparatus, systems and articles of manufacture to reduce bank pressure using aggressive write merging are disclosed. An example apparatus includes a first cache storage; a second cache storage; a store queue coupled to at least one of the first cache storage and the second cache storage and operable to: receive a first memory operation; process the first memory operation for storing the first set of data in at least one of the first cache storage and the second cache storage; receive a second memory operation; and prior to storing the first set of data in the at least one of the first cache storage and the second cache storage, merge the first memory operation and the second memory operation.
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公开(公告)号：US20180136707A1
公开(公告)日：2018-05-17
申请号：US15868299
申请日：2018-01-11
发明人： Chang Wan Ha , Hang Tian , Jong Kang
CPC分类号： G06F1/324 , G06F1/12 , G06F1/3237 , G06F1/3275 , G06F13/1673 , G11C7/1015 , G11C7/222 , Y02B70/12 , Y02B70/123 , Y02B70/126 , Y02D10/128 , Y02D10/13 , Y02D10/14
摘要： Apparatus facilitating peak power management include a plurality of dies, with each such die comprising an array of memory cells, a controller for performing access operations on the array of memory cells, and a counter configured to be responsive to a clock signal. A particular die of a first subset of dies of the plurality of dies comprises a clock generator for generating the clock signal. Each die of the first subset of dies is configured to be selectively enabled to receive commands in response to a first chip enable signal, and each die of a second subset of dies of the plurality of dies is configured to be selectively enabled to receive commands in response to a second chip enable signal independent of the first chip enable signal, wherein the first subset of dies and the second subset of dies are mutually exclusive.
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公开(公告)号：US20170309323A1
公开(公告)日：2017-10-26
申请号：US15595056
申请日：2017-05-15
IPC分类号： G11C11/4076 , G11C7/22 , G11C7/10 , G11C8/10
CPC分类号： G11C8/18 , G11C7/1015 , G11C7/1057 , G11C7/1066 , G11C7/1069 , G11C7/1084 , G11C7/1087 , G11C7/1093 , G11C7/1096 , G11C7/22 , G11C7/222 , G11C7/225 , G11C8/10 , G11C11/4076 , G11C29/023 , G11C29/024 , G11C29/028 , G11C2207/2254 , G11C2207/2272
摘要： Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.
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公开(公告)号：US09792052B2
公开(公告)日：2017-10-17
申请号：US15272933
申请日：2016-09-22
发明人： John K. Debrosse , Blake G. Fitch , Michele M. Franceschini , Todd E. Takken , Daniel C. Worledge
CPC分类号： G06F3/0613 , G06F3/0602 , G06F3/061 , G06F3/0656 , G06F3/0659 , G06F3/0673 , G06F3/0679 , G06F3/0688 , G06F13/1668 , G11C7/10 , G11C7/1003 , G11C7/1015 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069
摘要： A memory includes multiple non-volatile memory devices, each having multiple nonvolatile memory cells. A write controller is configured to stream bits to the memory devices using a write data channel that optimizes a speed of writing to the memory devices to provide writes at a first speed. A read controller is configured to read bits from the memory devices, at a second speed slower than the first speed, using a read channel. A bi-directional bus that both the write controller and the self-referenced read controller share to access the plurality of non-volatile memory devices.
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