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公开(公告)号:US20180323767A1
公开(公告)日:2018-11-08
申请号:US15773016
申请日:2015-12-04
Applicant: INTEL CORPORATION
Inventor: HAN WUI THEN , SANSAPTAK DASGUPTA , MARKO RADOSAVLJEVIC
CPC classification number: H03H9/173 , H03H3/02 , H03H9/02015 , H03H9/13 , H03H9/174 , H03H9/562 , H03H2003/021 , H03H2003/023
Abstract: Techniques are disclosed for forming high frequency film bulk acoustic resonator (FBAR) devices using epitaxially grown piezoelectric films. In some cases, the piezoelectric layer of the FBAR may be an epitaxial III-V layer such as an aluminum nitride (AlN) or other group III material-nitride (III-N) compound film grown as a part of a III-V material stack, although any other suitable piezoelectric materials can be used. Use of an epitaxial piezoelectric layer in an FBAR device provides numerous benefits, such as being able to achieve films that are thinner and higher quality compared to sputtered films, for example. The higher quality piezoelectric film results in higher piezoelectric coupling coefficients, which leads to higher Q-factor of RF filters including such FBAR devices. Therefore, the FBAR devices can be included in RF filters to enable filtering high frequencies of greater than 3 GHz, which can be used for 5G wireless standards, for example.
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公开(公告)号:US20180175184A1
公开(公告)日:2018-06-21
申请号:US15576508
申请日:2015-06-26
Applicant: INTEL CORPORATION
Inventor: HAN WUI THEN , SANSAPTAK DASGUPTA , SANAZ K. GARDNER , MARKO RADOSAVLJEVIC , SEUNG HOON SUNG , ROBERT S. CHAU
IPC: H01L29/778 , H01L29/78 , H01L29/20
CPC classification number: H01L29/7786 , H01L21/76248 , H01L29/2003 , H01L29/42392 , H01L29/66742 , H01L29/775 , H01L29/7783 , H01L29/78 , H01L29/785 , H01L29/78681
Abstract: Techniques are disclosed for gallium nitride (GaN) oxide isolation and formation of GaN transistor structures on a substrate. In some cases, the GaN transistor structures can be used for system-on-chip integration of high-voltage GaN front-end radio frequency (RF) switches on a bulk silicon substrate. The techniques can include, for example, forming multiple fins in a substrate, depositing the GaN layer on the fins, oxidizing at least a portion of each fin in a gap below the GaN layer, and forming one or more transistors on and/or from the GaN layer. In some cases, the GaN layer is a plurality of GaN islands, each island corresponding to a given fin. The techniques can be used to form various non-planar isolated GaN transistor architectures having a relatively small form factor, low on-state resistance, and low off-state leakage, in some cases.
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