公开(公告)号：US20170358645A1

公开(公告)日：2017-12-14

申请号：US15525269

申请日：2014-12-26

Applicant: INTEL CORPORATION

Inventor： GILBERT DEWEY ,  MATTHEW V. METZ ,  JACK T. KAVALIEROS ,  WILLY RACHMADY ,  TAHIR GHANI ,  ANAND S. MURTHY ,  CHANDRA S. MOHAPATRA ,  SANAZ K. GARDNER ,  MARKO RADOSAVLJEVIC ,  GLENN A. GLASS

IPC: H01L29/06 ,  H01L29/12 ,  H01L29/66 ,  H01L21/762 ,  H01L21/311 ,  H01L29/78 ,  H01L29/775 ,  H01L21/306 ,  H01L21/02 ,  H01L29/20 ,  H01L29/161 ,  H01L29/04

CPC classification number: H01L29/0673 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/7605 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/122 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66469 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: An integrated circuit die includes a quad-gate device nanowire of channel material for a transistor (e.g., single material or stack to be a channel of a MOS device) formed by removing a portion of a sub-fin material from below the channel material, where the sub-fin material was grown in an aspect ration trapping (ART) trench. In some cases, in the formation of such nanowires, it is possible to remove the defective fin material or area under the channel. Such removal isolates the fin channel, removes the fin defects and leakage paths, and forms the nanowire of channel material having four exposed surfaces upon which gate material may be formed.

公开(公告)号：US20180170747A1

公开(公告)日：2018-06-21

申请号：US15576510

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  SANAZ K. GARDNER ,  RAVI PILLARISETTY ,  MARKO RADOSAVLJEVIC ,  SEUNG HOON SUNG ,  ROBERT S. CHAU

IPC: B81C1/00 ,  B81B7/02 ,  B81B3/00

CPC classification number: B81C1/00246 ,  B81B3/0021 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C2203/0714 ,  G01L1/18

Abstract: Techniques are disclosed for forming group III material-nitride (III-N) microelectromechanical systems (MEMS) structures on a group IV substrate, such as a silicon, silicon germanium, or germanium substrate. In some cases, the techniques include forming a III-N layer on the substrate and optionally on shallow trench isolation (STI) material, and then releasing the III-N layer by etching to form a free portion of the III-N layer suspended over the substrate. The techniques may include, for example, using a wet etch process that selectively etches the substrate and/or STI material, but does not etch the III-N material (or etches the III-N material at a substantially slower rate). Piezoresistive elements can be formed on the III-N layer to, for example, detect vibrations or deflection in the free/suspended portion of the III-N layer. Accordingly, MEMS sensors can be formed using the techniques, such as accelerometers, gyroscopes, and pressure sensors, for example.

公开(公告)号：US20190058042A1

公开(公告)日：2019-02-21

申请号：US16080100

申请日：2016-03-30

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC ,  SANAZ K. GARDNER ,  SEUNG HOON SUNG

IPC: H01L29/20 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/778

Abstract: Techniques are disclosed for forming transistors including retracted raised source/drain (S/D) to reduce parasitic capacitance. In some cases, the techniques include forming ledges for S/D epitaxial regrowth on a high-quality crystal nucleation surface. The techniques may also include forming the raised sections of the S/D regions (e.g., the portions adjacent to spacer material between the S/D regions and the gate material) in a manner such that the S/D raised sections are retracted from the gate material. This can be achieved by forming a notch at the interface between a polarization charge inducing layer and an oxide layer using a wet etch process, such that a relatively high-quality surface of the polarization charge inducing layer material is exposed for S/D regrowth. Therefore, the benefits derived from growing the S/D material from a high-quality nucleation surface can be retained while reducing the parasitic overlap capacitance penalty that would otherwise be present.

公开(公告)号：US20180342985A1

公开(公告)日：2018-11-29

申请号：US15777744

申请日：2015-12-21

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC ,  SEUNG HOON SUNG ,  SANAZ K. GARDNER

IPC: H03F1/02 ,  H03F3/195 ,  H03F3/213 ,  H01L29/20 ,  H01L29/205 ,  H01L29/49 ,  H01L29/51 ,  H01L29/778 ,  H01L23/66

CPC classification number: H03F1/0222 ,  H01L23/66 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7786 ,  H01L29/7787 ,  H03F3/193 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/102 ,  H03F2200/105 ,  H03F2200/15 ,  H03F2200/18 ,  H03F2200/451

Abstract: Envelope-tracking control techniques are disclosed for highly-efficient radio frequency (RF) power amplifiers. In some cases, a III-V semiconductor material (e.g., GaN or other group III material-nitride (III-N) compounds) MOSFET including a high-k gate dielectric may be used to achieve such highly-efficient RF power amplifiers. The use of a high-k gate dielectric can help to ensure low gate leakage and provide high input impedance for RF power amplifiers. Such high input impedance enables the use of envelope-tracking control techniques that include gate voltage (Vg) modulation of the III-V MOSFET used for the RF power amplifier. In such cases, being able to modulate Vg of the RF power amplifier using, for example, a voltage regulator, can result in double-digit percentage gains in power-added efficiency (PAE). In some instances, the techniques may simultaneously utilize envelope-tracking control techniques that include drain voltage (Vd) modulation of the III-V MOSFET used for the RF power amplifier.

公开(公告)号：US20180175184A1

公开(公告)日：2018-06-21

申请号：US15576508

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  SANAZ K. GARDNER ,  MARKO RADOSAVLJEVIC ,  SEUNG HOON SUNG ,  ROBERT S. CHAU

IPC: H01L29/778 ,  H01L29/78 ,  H01L29/20

CPC classification number: H01L29/7786 ,  H01L21/76248 ,  H01L29/2003 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7783 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78681

Abstract: Techniques are disclosed for gallium nitride (GaN) oxide isolation and formation of GaN transistor structures on a substrate. In some cases, the GaN transistor structures can be used for system-on-chip integration of high-voltage GaN front-end radio frequency (RF) switches on a bulk silicon substrate. The techniques can include, for example, forming multiple fins in a substrate, depositing the GaN layer on the fins, oxidizing at least a portion of each fin in a gap below the GaN layer, and forming one or more transistors on and/or from the GaN layer. In some cases, the GaN layer is a plurality of GaN islands, each island corresponding to a given fin. The techniques can be used to form various non-planar isolated GaN transistor architectures having a relatively small form factor, low on-state resistance, and low off-state leakage, in some cases.

公开(公告)号：US20190221660A1

公开(公告)日：2019-07-18

申请号：US16306292

申请日：2016-07-01

Applicant: INTEL CORPORATION

Inventor： SANSAPTAK DASGUPTA ,  HAN WUI THEN ,  MARKO RADOSAVLJEVIC ,  SANAZ K. GARDNER ,  SEUNG HOON SUNG

IPC: H01L29/778 ,  H01L29/51 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/432 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7786

Abstract: A gate stack structure is disclosed for inhibiting charge leakage in III-V transistor devices. The techniques are particularly well-suited for use in enhancement-mode MOSHEMTs, but can also be used in other transistor designs susceptible to charge spillover and unintended channel formation in the gate stack. In an example embodiment, the techniques are realized in a transistor having a III-N gate stack over a gallium nitride (GaN) channel layer. The gate stack is configured with a relatively thick barrier structure and wide bandgap III-N materials to prevent or otherwise reduce channel charge spillover resulting from tunneling or thermionic processes at high gate voltages. The barrier structure is configured to manage lattice mismatch conditions, so as to provide a robust high performance transistor design. In some cases, the gate stack is used in conjunction with an access region polarization layer to induce two-dimensional electron gas (2DEG) in the channel layer.

公开(公告)号：US20180331182A1

公开(公告)日：2018-11-15

申请号：US15774064

申请日：2015-12-07

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC ,  SANAZ K. GARDNER ,  SEUNG HOON SUNG

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/267

CPC classification number: H01L29/0847 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/785

Abstract: Techniques are disclosed for forming self-aligned transistor structures including two-dimensional electron gas (2DEG) source/drain tip portions or tips. In some cases, the 2DEG source/drain tips utilize polarization doping to enable ultra-short transistor channel lengths of less than 20 nm, for example, and create highly conductive, thin source/drain tip portions in transistor devices. In some instances, the 2DEG source/drain tips can be formed by self-aligned regrowth of a polarization layer over a base III-V compound layer and on either side of a dummy gate, in locations to be substantially covered by spacers. In some cases, the III-V base layer may include gallium nitride (GaN) or indium gallium nitride (InGaN), for example, and the polarization layer may include aluminum indium nitride (AlInN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or aluminum indium gallium nitride (AlInGaN), for example.

公开(公告)号：US20160204207A1

公开(公告)日：2016-07-14

申请号：US14913173

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC ,  ROBERT S. CHAU ,  SEUNG HOON SUNG ,  SANAZ K. GARDNER

IPC: H01L29/20 ,  H01L29/207 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/786 ,  H01L29/51 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0254 ,  H01L21/28264 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66484 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78696

Abstract: Enhancement mode gallium nitride (GaN) semiconductor devices having a composite high-k metal gate stack and methods of fabricating such devices are described. In an example, a semiconductor device includes a gallium nitride (GaN) channel region disposed above a substrate. A gate stack is disposed on the GaN channel region. The gate stack includes a composite gate dielectric layer disposed directly between the GaN channel region and a gate electrode. The composite gate dielectric layer includes a high band gap Group III-N layer, a first high-K dielectric oxide layer, and a second high-K dielectric oxide layer having a higher dielectric constant than the first high-K dielectric oxide layer. Source/drain regions are disposed on either side of the GaN channel region.

Abstract translation: 描述了具有复合高k金属栅叠层的增强模式氮化镓（GaN）半导体器件及其制造方法。 在一个示例中，半导体器件包括设置在衬底上方的氮化镓（GaN）沟道区。 栅叠层设置在GaN沟道区上。 栅极堆叠包括直接设置在GaN沟道区和栅电极之间的复合栅介质层。 复合栅极电介质层包括具有比第一高K电介质氧化物层更高的介电常数的高带隙组III-N层，第一高K电介质氧化物层和第二高K电介质氧化物层。 源/漏区设置在GaN沟道区的两侧。