公开(公告)号：US11553446B2

公开(公告)日：2023-01-10

申请号：US17346024

申请日：2021-06-11

Applicant: Intel Corporation

Inventor： Kishore Kasichainula

IPC: H04W56/00 ,  G05B19/042

Abstract: Technologies for managing internal time synchronization include an internet-of-things (IoT) device configured to determine a transport delay value as a function of a transmit path delay corresponding to a first message transmitted from an I/O device of the IoT device to a central timer of the IoT device and a receive path delay corresponding to a second message transmitted from the central timer to the I/O device. The IoT device is further configured to update, in response to having received a broadcast message from the central timer subsequent to having determined the transport delay value, a timestamp value of the received broadcast message as a function of the transport delay value. Other embodiments are described herein.

公开(公告)号：US20210328944A1

公开(公告)日：2021-10-21

申请号：US17359139

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Kishore Kasichainula

IPC: H04L12/861 ,  H04L29/08

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to dynamically allocate cache. An example includes a cache having a queue, data stream classification circuitry, and cache management circuitry. In an example, the data stream classification circuitry is configured to decode a data stream assigned to the queue of the cache to determine a traffic class assigned to the queue. In additional or alternative examples, the cache management circuitry is configured to, based on the traffic class assigned to the queue, allocate a portion of the cache to the queue. In some examples, the cache management circuitry is configured to transmit a signal to a memory controller to adjust allocation of the cache.

公开(公告)号：US20210014177A1

公开(公告)日：2021-01-14

申请号：US17033722

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Kishore Kasichainula

IPC: H04L12/879 ,  G06F13/28 ,  H04L12/851 ,  H04L12/863 ,  H04L12/46

Abstract: In one embodiment, a network interface controller (NIC) includes multiple packet transmission queues to queue data packets for transmission. The data packets are assigned to multiple traffic classes. The NIC also includes multiple input/output (I/O) interfaces for retrieving the data packets from memory. Each I/O interface is assigned to a subset of the traffic classes. The NIC also includes scheduler circuitry to select a first data packet to be retrieved from memory, and direct memory access (DMA) engine circuitry to retrieve the first data packet from memory via one of the I/O interfaces based on the traffic class of the first data packet, and store the first data packet in one of the packet transmission queues. The NIC also includes a transmission interface to transmit the first data packet over a network at a corresponding launch time indicated by the scheduler circuitry.

公开(公告)号：US10754816B2

公开(公告)日：2020-08-25

申请号：US16230829

申请日：2018-12-21

Applicant: INTEL CORPORATION

Inventor： Kishore Kasichainula

IPC: G06F15/173 ,  H04L12/46 ,  H04L12/863 ,  H04L12/875

Abstract: The present disclosure generally relates to a device, method, or system for time sensitive networking. In an example, the device can include a time-sensitive networking controller and a scheduler. The device also includes an enhanced gate control list maintained on the time-sensitive networking controller to include a direct memory access address, a launch time, and a pre-fetch time for a data packet. The device may also include a transmitter of the time-sensitive networking controller to transmit the data packet retrieved using the direct memory access address at the launch time identified by the scheduler.

公开(公告)号：US20190121781A1

公开(公告)日：2019-04-25

申请号：US16230829

申请日：2018-12-21

Applicant: INTEL CORPORATION

Inventor： Kishore Kasichainula

IPC: G06F15/173 ,  H04L12/863 ,  H04L12/46

CPC classification number: G06F15/17331 ,  H04L12/4645 ,  H04L47/564 ,  H04L47/6215

Abstract: The present disclosure generally relates to a device, method, or system for time sensitive networking. In an example, the device can include a time-sensitive networking controller and a scheduler. The device also includes an enhanced gate control list maintained on the time-sensitive networking controller to include a direct memory access address, a launch time, and a pre-fetch time for a data packet. The device may also include a transmitter of the time-sensitive networking controller to transmit the data packet retrieved using the direct memory access address at the launch time identified by the scheduler.