公开(公告)号：US11856546B2

公开(公告)日：2023-12-26

申请号：US18151951

申请日：2023-01-09

Applicant: Intel Corporation

Inventor： Kishore Kasichainula

IPC: H04W56/00 ,  G05B19/042

CPC classification number: H04W56/0065 ,  G05B19/0423 ,  H04W56/003 ,  H04W56/0015

Abstract: Technologies for managing internal time synchronization include an internet-of-things (IoT) device configured to determine a transport delay value as a function of a transmit path delay corresponding to a first message transmitted from an I/O device of the IoT device to a central timer of the IoT device and a receive path delay corresponding to a second message transmitted from the central timer to the I/O device. The IoT device is further configured to update, in response to having received a broadcast message from the central timer subsequent to having determined the transport delay value, a timestamp value of the received broadcast message as a function of the transport delay value. Other embodiments are described herein.

公开(公告)号：US20230396555A1

公开(公告)日：2023-12-07

申请号：US18234622

申请日：2023-08-16

Applicant: Intel Corporation

Inventor： Kishore Kasichainula

IPC: H04L47/2408 ,  H04L12/46 ,  H04L47/6275

CPC classification number: H04L47/2408 ,  H04L12/4641 ,  H04L47/6275

Abstract: A network interface device for implementing scheduling for time sensitive networking includes a network interface device comprising media access control (MAC) circuitry, including a priority router to parse a packet payload to determine a priority value; determine a corresponding traffic class based on the priority value from the packet payload; and route the packet payload to one of a plurality of traffic class-based packet buffers based on the traffic class; and a packet router to: retrieve a packet payload from the plurality of traffic class-based packet buffers based on the traffic class; and place the packet payload in a queue for a direct memory access (DMA) circuitry to store the packet payload in main memory.

公开(公告)号：US20230284168A1

公开(公告)日：2023-09-07

申请号：US18151951

申请日：2023-01-09

Applicant: Intel Corporation

Inventor： Kishore Kasichainula

IPC: H04W56/00 ,  G05B19/042

CPC classification number: H04W56/0065 ,  G05B19/0423 ,  H04W56/003 ,  H04W56/0015

Abstract: Technologies for managing internal time synchronization include an internet-of-things (IoT) device configured to determine a transport delay value as a function of a transmit path delay corresponding to a first message transmitted from an I/O device of the IoT device to a central timer of the IoT device and a receive path delay corresponding to a second message transmitted from the central timer to the I/O device. The IoT device is further configured to update, in response to having received a broadcast message from the central timer subsequent to having determined the transport delay value, a timestamp value of the received broadcast message as a function of the transport delay value. Other embodiments are described herein.

公开(公告)号：US20230262281A1

公开(公告)日：2023-08-17

申请号：US18296264

申请日：2023-04-05

Applicant: Intel Corporation

Inventor： Kishore Kasichainula ,  Aswin Padmanabhan ,  Satyeshwar Singh

IPC: H04N21/43

CPC classification number: H04N21/43076

Abstract: The present disclosure provides display network synchronization (sync) technologies and techniques using time-sensitive networking (TSN) and/or Precision Time Protocol (PTP) technologies. The display network sync mechanisms synchronize multiple display systems that are communicatively coupled together via a network. The display network sync mechanisms involve synchronizing the display systems with one another, synchronizing the various clocks and/or timers of each display system, monitoring clock drift of display clocks of individual display systems, and adjusting display signaling based on the monitored clock drift. The monitoring and adjusting of the display signaling can be accomplished without broadcasting the display signaling over the network connection.

公开(公告)号：US20220224624A1

公开(公告)日：2022-07-14

申请号：US17709639

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Kishore Kasichainula

IPC: H04L43/106 ,  H04L43/0894 ,  H04L41/0896

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve bandwidth for packet timestamping. An example apparatus includes cache to store a pointer, the pointer indicative of an address in shared memory where a timestamp is to be stored, the pointer corresponding to a descriptor of data to be transmitted to a second device. The example apparatus also includes memory access control circuitry to parse the descriptor to determine the pointer and cause storage of the pointer in the cache. Additionally, the memory access control circuitry of the example apparatus is to set a control bit of the descriptor to indicate that the descriptor may be overwritten.

公开(公告)号：US20220188263A1

公开(公告)日：2022-06-16

申请号：US17561801

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Kishore Kasichainula

IPC: G06F15/173 ,  H04L12/46 ,  H04L47/62 ,  H04L47/56

Abstract: The present disclosure generally relates to a device, method, or system for time sensitive networking. In an example, the device can include a time-sensitive networking controller and a scheduler. The device also includes an enhanced gate control list maintained on the time-sensitive networking controller to include a direct memory access address, a launch time, and a pre-fetch time for a data packet. The device may also include a transmitter of the time-sensitive networking controller to transmit the data packet retrieved using the direct memory access address at the launch time identified by the scheduler.

公开(公告)号：US20210320886A1

公开(公告)日：2021-10-14

申请号：US17357682

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Kishore Kasichainula

IPC: H04L12/861

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for deterministic low latency packet forwarding for daisy chaining of network devices. An example apparatus includes fabric circuitry, first data interface circuitry and second data interface circuitry coupled to the fabric circuitry, the first data interface circuitry to, in response to a receipt of a data packet, identify the data packet to be transmitted to third data interface circuitry, a data forwarding buffer, and packet forwarding engine circuitry coupled to the data forwarding buffer and the fabric circuitry, the packet forwarding engine circuitry to store the data packet in the data forwarding buffer, and instruct the second data interface circuitry to transmit the data packet from the data forwarding buffer to the third data interface circuitry.

公开(公告)号：US20230098298A1

公开(公告)日：2023-03-30

申请号：US18074842

申请日：2022-12-05

Applicant: Intel Corporation

Inventor： Kishore Kasichainula

IPC: H04L1/00

Abstract: A driver of an Ethernet controller may determine, based on an interrupt received from a PHY circuit coupled to the Ethernet controller, that a connection between the PHY circuit and a remote device was established using auto-negotiation over a physical communication medium. The driver may determine a speed of the connection. The driver may, based on a determination that the speed of the connection is not a first predetermined speed, enable auto-negotiation between the PHY circuit and the Ethernet controller to establish a link at a second speed that is different than the first predetermined speed.

公开(公告)号：US20220141790A1

公开(公告)日：2022-05-05

申请号：US17346024

申请日：2021-06-11

Applicant: Intel Corporation

Inventor： Kishore Kasichainula

IPC: H04W56/00 ,  G05B19/042

Abstract: Technologies for managing internal time synchronization include an internet-of-things (IoT) device configured to determine a transport delay value as a function of a transmit path delay corresponding to a first message transmitted from an I/O device of the IoT device to a central timer of the IoT device and a receive path delay corresponding to a second message transmitted from the central timer to the I/O device. The IoT device is further configured to update, in response to having received a broadcast message from the central timer subsequent to having determined the transport delay value, a timestamp value of the received broadcast message as a function of the transport delay value. Other embodiments are described herein.

公开(公告)号：US11057857B2

公开(公告)日：2021-07-06

申请号：US16145320

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Kishore Kasichainula

IPC: H04W56/00 ,  G05B19/042

Abstract: Technologies for managing internal time synchronization include an internet-of-things (IoT) device configured to determine a transport delay value as a function of a transmit path delay corresponding to a first message transmitted from an I/O device of the IoT device to a central timer of the IoT device and a receive path delay corresponding to a second message transmitted from the central timer to the I/O device. The IoT device is further configured to update, in response to having received a broadcast message from the central timer subsequent to having determined the transport delay value, a timestamp value of the received broadcast message as a function of the transport delay value. Other embodiments are described herein.