公开(公告)号：US20240333471A1

公开(公告)日：2024-10-03

申请号：US18190308

申请日：2023-03-27

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Sanu Mathew ,  Sachin Taneja

IPC: H04L9/06

CPC classification number: H04L9/0631 ,  H04L9/0637

Abstract: In one embodiment, a method comprises: combining, in a first adder circuit of a cryptographic engine, a round key with masked plaintext to generate an additively masked input; converting, in a first converter of the cryptographic engine, the additively masked input to a multiplicatively masked input; and performing, in a substitution box circuit of the cryptographic engine, a non-linear inverse operation on the multiplicatively masked input when the multiplicatively masked input is non-zero, and performing the non-linear inverse operation on a random non-zero value when the multiplicatively masked input is zero. Other embodiments are described and claimed.

公开(公告)号：US20240007267A1

公开(公告)日：2024-01-04

申请号：US17810019

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Sanu K. Mathew

IPC: H04L9/06

CPC classification number: H04L9/0631 ,  H04L9/0656

Abstract: In one example an apparatus comprises a first input node to receive a first plaintext input, a second input node to receive a second plaintext input, a third input node to receive a random mask and an advanced encryption standard (AES) circuitry configurable to operate in one of a first mode in which the random mask is added to the first plaintext input during one or more computations to convert the first plaintext input to a first ciphertext output, or a second mode in which the first plaintext input is converted to a first ciphertext output and the second plaintext input is converted to a second ciphertext output without using the random mask. Other examples may be described.

公开(公告)号：US20240007266A1

公开(公告)日：2024-01-04

申请号：US17809997

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Vikram B. Suresh ,  Sanu K. Mathew

IPC: H04L9/06 ,  H04L9/00

CPC classification number: H04L9/0631 ,  H04L9/50

Abstract: In one example an apparatus comprises a first input node to receive a first plaintext input, a second input node to receive a random mask, an advanced encryption standard (AES) engine configurable to operate in one of a first mode in which the random mask is added to the first plaintext input during one or more computations performed by the AES engine, or second mode in which the random mask is not added to the first plaintext input during one or more computations performed by the AES engine. Other examples may be described.

公开(公告)号：US11751404B2

公开(公告)日：2023-09-05

申请号：US16141025

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Gregory Chen ,  Phil Knag ,  Ram Krishnamurthy ,  Raghavan Kumar ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Huseyin Sumbul ,  Ian A. Young

IPC: H01L27/24 ,  H10B63/00 ,  H01L29/78 ,  H01L29/66 ,  H10N70/00

CPC classification number: H10B63/30 ,  H01L29/66795 ,  H01L29/785 ,  H10N70/021 ,  H10N70/826 ,  H10N70/882 ,  H10N70/8833

Abstract: Embodiments herein describe techniques for a semiconductor device including a RRAM memory cell. The RRAM memory cell includes a FinFET transistor and a RRAM storage cell. The FinFET transistor includes a fin structure on a substrate, where the fin structure includes a channel region, a source region, and a drain region. An epitaxial layer is around the source region or the drain region. A RRAM storage stack is wrapped around a surface of the epitaxial layer. The RRAM storage stack includes a resistive switching material layer in contact and wrapped around the surface of the epitaxial layer, and a contact electrode in contact and wrapped around a surface of the resistive switching material layer. The epitaxial layer, the resistive switching material layer, and the contact electrode form a RRAM storage cell. Other embodiments may be described and/or claimed.

公开(公告)号：US11625584B2

公开(公告)日：2023-04-11

申请号：US16443548

申请日：2019-06-17

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Gregory K. Chen ,  Huseyin Ekin Sumbul ,  Phil Knag ,  Ram Krishnamurthy

IPC: G06N3/063 ,  G06N3/084 ,  G06F7/544

Abstract: Examples described herein relate to a neural network whose weights from a matrix are selected from a set of weights stored in a memory on-chip with a processing engine for generating multiply and carry operations. The number of weights in the set of weights stored in the memory can be less than a number of weights in the matrix thereby reducing an amount of memory used to store weights in a matrix. The weights in the memory can be generated in training using gradients from back propagation. Weights in the memory can be selected using a tabulation hash calculation on entries in a table.

公开(公告)号：US11347477B2

公开(公告)日：2022-05-31

申请号：US16586648

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Phil Knag ,  Raghavan Kumar ,  Ram Krishnamurthy

IPC: G06F7/544 ,  G06F17/16 ,  G06F7/498 ,  G06F12/02 ,  G06F9/30

Abstract: A memory circuit includes a number (X) of multiply-accumulate (MAC) circuits that are dynamically configurable. The MAC circuits can either compute an output based on computations of X elements of the input vector with the weight vector, or to compute the output based on computations of a single element of the input vector with the weight vector, with each element having a one bit or multibit length. A first memory can hold the input vector having a width of X elements and a second memory can store the weight vector. The MAC circuits include a MAC array on chip with the first memory.

公开(公告)号：US20220131706A1

公开(公告)日：2022-04-28

申请号：US17568919

申请日：2022-01-05

Applicant: Intel Corporation

Inventor： Rafael Misoczki ,  Vikram Suresh ,  Santosh Ghosh ,  Manoj Sastry ,  Sanu Mathew ,  Raghavan Kumar

IPC: H04L9/32 ,  H04L9/08

Abstract: In one example an apparatus comprises a computer-readable memory, signature logic to compute a message hash of an input message using a secure hash algorithm, process the message hash to generate an array of secret key components for the input message, apply a hash chain function to the array of secret key components to generate an array of signature components, the hash chain function comprising a series of even-index hash chains and a series of odd-index hash chains, wherein the even-index hash chains and the odd-index hash chains generate a plurality of intermediate node values and a one-time public key component between the secret key components and the signature components and store at least some of the intermediate node values in the computer-readable memory for use in one or more subsequent signature operations. Other examples may be described.

公开(公告)号：US11223483B2

公开(公告)日：2022-01-11

申请号：US16456064

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Rafael Misoczki ,  Vikram Suresh ,  Santosh Ghosh ,  Manoj Sastry ,  Sanu Mathew ,  Raghavan Kumar

IPC: H04L9/32 ,  H04L9/08

Abstract: In one example an apparatus comprises a computer-readable memory, signature logic to compute a message hash of an input message using a secure hash algorithm, process the message hash to generate an array of secret key components for the input message, apply a hash chain function to the array of secret key components to generate an array of signature components, the hash chain function comprising a series of even-index hash chains and a series of odd-index hash chains, wherein the even-index hash chains and the odd-index hash chains generate a plurality of intermediate node values and a one-time public key component between the secret key components and the signature components and store at least some of the intermediate node values in the computer-readable memory for use in one or more subsequent signature operations. Other examples may be described.

公开(公告)号：US11151046B2

公开(公告)日：2021-10-19

申请号：US16921685

申请日：2020-07-06

Applicant: Intel Corporation

Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young ,  Abhishek Sharma

IPC: G06F12/0875 ,  G06N3/063 ,  G06N3/04 ,  G06F3/06 ,  G06F8/41 ,  G06F9/455

Abstract: The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of in-memory vector/tensor calculations in furtherance of neural network processing without burdening the processor circuitry.

公开(公告)号：US11017288B2

公开(公告)日：2021-05-25

申请号：US15845245

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Ram Kumar Krishnamurthy ,  Gregory Kengho Chen ,  Raghavan Kumar ,  Phil Christopher Knag ,  Huseyin Ekin Sumbul

IPC: G06N3/04 ,  G06N3/08 ,  G06N3/063

Abstract: System and techniques for spike timing dependent plasticity (STDP) in neuromorphic hardware are described herein. A first spike may be received, at a first neuron at a first time, from a second neuron. The first neuron may produce a second spike at a second time after the first time. At a third time after the second time, the first neuron may receive a third spike from the second neuron. Here, the third spike is a replay of the first spike with a defined time offset. The first neuron may then perform long term potentiation (LTP) for the first spike using the third spike.