公开(公告)号：US11126374B2

公开(公告)日：2021-09-21

申请号：US16367323

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Jawad B. Khan ,  Richard Coulson

IPC: G06F3/06

Abstract: Technologies for stochastic associative search operations in memory (e.g., a three-dimensional cross-point memory) include a compute device. The compute device has a memory including a matrix that stores individually addressable bit data and is formed by rows and columns. The compute device receives a request to retrieve a subset of the bit data stored in the matrix. The request includes a search key indicative of the subset of bit data, and the search key is formed on a same axis as the rows. The compute device identifies one or more candidate data sets in the matrix based on a search for matching bit data of the search key with bit data in one or more of the columns. The compute device outputs the identified candidate data sets.

公开(公告)号：US10942847B2

公开(公告)日：2021-03-09

申请号：US16223539

申请日：2018-12-18

Applicant: Intel Corporation

Inventor： Jawad B. Khan ,  Richard Coulson

IPC: G06F12/02 ,  G06F12/0866 ,  G11C13/00

Abstract: Technologies for efficiently performing scatter-gather operations include a device with circuitry configured to associate, with a template identifier, a set of non-contiguous memory locations of a memory having a cross point architecture. The circuitry is additionally configured to access, in response to a request that identifies the non-contiguous memory locations by the template identifier, the memory locations.

公开(公告)号：US20190220400A1

公开(公告)日：2019-07-18

申请号：US16367321

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Jawad B. Khan ,  Richard Coulson

IPC: G06F12/06

CPC classification number: G06F12/06 ,  G06F2212/1041

Abstract: Technologies for addressing individual bits in memory include a device having a memory that includes partitions that each have tiles, in which each tile stores an individual bit. The device also includes circuitry to receive a request to access (e.g., read or write) a sequence of bits in a partition. The request specifies a logical row or column address. A corresponding tile is determined from the logical row or column address and for each bit in the sequence. The corresponding tile is accessed to read or write the bit therein.

公开(公告)号：US20190146717A1

公开(公告)日：2019-05-16

申请号：US16249964

申请日：2019-01-17

Applicant: Intel Corporation

Inventor： Jawad B. Khan ,  Richard Coulson

IPC: G06F3/06 ,  G06F12/06

Abstract: Technologies for efficiently accessing data columns and rows in a memory include a device with circuitry configured to receive a request to access memory in which each bit of a logical column of bits is located in a different physical row and a different physical column than any other bit in the logical column. The circuitry is additionally configured to access, in response to the request, the memory. In accessing the memory, the circuitry rotates one or more bit positions in a data set read from or written to the memory