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    TECHNOLOGIES FOR ADDING COMPUTATIONAL ABILITY TO MEMORY DEVICES WITHOUT CHANGING MEDIA LAYERS
    1.
    发明申请
    TECHNOLOGIES FOR ADDING COMPUTATIONAL ABILITY TO MEMORY DEVICES WITHOUT CHANGING MEDIA LAYERS 审中-公开

    公开(公告)号：US20190294567A1

    公开(公告)日：2019-09-26

    申请号：US16435861

    申请日：2019-06-10

    Applicant: Intel Corporation

    Inventor： Jawad B. Khan ,  Richard Coulson

    IPC: G06F13/16 ,  G06F13/40

    Abstract: Technologies for adding computational ability to memory devices without changing media layers include a process for the manufacture of a memory device. The process includes obtaining a memory media capable of communicating with multiple different types of media access circuitries through a set of communication paths at predefined locations. The process also includes obtaining a media access circuitry capable of communicating with the memory media through the communication paths at the predefined locations and connecting the obtained memory media to the obtained media access circuitry to enable communication through the communication paths at the predefined locations.

    TECHNOLOGIES FOR EFFICIENT STOCHASTIC ASSOCIATIVE SEARCH OPERATIONS
    2.
    发明申请
    TECHNOLOGIES FOR EFFICIENT STOCHASTIC ASSOCIATIVE SEARCH OPERATIONS 审中-公开

    公开(公告)号：US20190220230A1

    公开(公告)日：2019-07-18

    申请号：US16367323

    申请日：2019-03-28

    Applicant: Intel Corporation

    Inventor： Jawad B. Khan ,  Richard Coulson

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0673

    Abstract: Technologies for stochastic associative search operations in memory (e.g., a three-dimensional cross-point memory) include a compute device. The compute device has a memory including a matrix that stores individually addressable bit data and is formed by rows and columns. The compute device receives a request to retrieve a subset of the bit data stored in the matrix. The request includes a search key indicative of the subset of bit data, and the search key is formed on a same axis as the rows. The compute device identifies one or more candidate data sets in the matrix based on a search for matching bit data of the search key with bit data in one or more of the columns. The compute device outputs the identified candidate data sets.

    Technologies for direct matrix read and write operations
    5.
    发明授权
    Technologies for direct matrix read and write operations 有权

    公开(公告)号：US11307977B2

    公开(公告)日：2022-04-19

    申请号：US16144459

    申请日：2018-09-27

    Applicant: Intel Corporation

    Inventor： Jawad B. Khan ,  Richard Coulson

    IPC: G06F12/02 ,  G06F3/06 ,  G06F15/78

    Abstract: Technologies for directly performing read and write operations on matrix data in a data storage device are disclosed. The data storage device receives a request to perform a read or write operation on matrix data stored in one or more memory units of the data storage device. Each memory unit is associated with a column address for the matrix data. The data storage device determines whether the request specifies to read or write a column or a row in the matrix data. The data storage device performs, in response to a determination that the request specifies to read or write a column in the matrix data, the read or write operation on the matrix data on the column.

    Technologies for efficient stochastic associative search operations with error-correcting code
    6.
    发明授权
    Technologies for efficient stochastic associative search operations with error-correcting code 有权

    公开(公告)号：US11262913B2

    公开(公告)日：2022-03-01

    申请号：US16367320

    申请日：2019-03-28

    Applicant: Intel Corporation

    Inventor： Jawad B. Khan ,  Richard Coulson

    IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C29/04

    Abstract: Technologies for stochastic associative search operations in memory (e.g., a three-dimensional cross-point memory) using error correction codes include a compute device. The compute device has a memory including a matrix that stores individually addressable bit data and is formed by rows and columns. The compute device receives a request to retrieve a subset of the bit data stored in the matrix. The compute device identifies, based on a search performed on the columns in the matrix, one or more candidate data sets. Each candidate data set corresponds to one of the rows in the matrix. The compute device performs an error correction operation on the identified one or more candidate data sets to determine whether the identified one or more candidate data sets is an exact match with the subset of the bit data.

    Technologies for efficient exit from hyper dimensional space in the presence of errors
    7.
    发明授权
    Technologies for efficient exit from hyper dimensional space in the presence of errors 有权

    公开(公告)号：US10949214B2

    公开(公告)日：2021-03-16

    申请号：US16370013

    申请日：2019-03-29

    Applicant: Intel Corporation

    Inventor： Jawad B. Khan ,  Richard Coulson

    IPC: G06F12/02 ,  G06F15/80 ,  G06F16/33 ,  G06F16/903 ,  G06F9/30 ,  G06F9/38 ,  G11C11/54 ,  G11C7/10

    Abstract: Technologies for performing hyper-dimensional operations in memory includes a device with a memory media and a memory controller. The memory controller is configured to receive a query from a requestor and determine, in response to receiving the query, a reference hyper-dimensional vector associated with the query. The memory controller is further configured to perform a nearest neighbor search by searching columns of a stochastic associative array in the memory media to determine a number of matching bit values for each row relative to the reference hyper-dimensional vector, wherein each bit in a column of the stochastic associative array represents a bit value of a corresponding row, identify a closest matching row that has a highest number of matching bit values, and output data of the closest matching row.

    TECHNOLOGIES FOR PERFORMING COLUMN ARCHITECTURE-AWARE SCRAMBLING
    8.
    发明申请
    TECHNOLOGIES FOR PERFORMING COLUMN ARCHITECTURE-AWARE SCRAMBLING 审中-公开

    公开(公告)号：US20200272340A1

    公开(公告)日：2020-08-27

    申请号：US15930035

    申请日：2020-05-12

    Applicant: Intel Corporation

    Inventor： Zion Kwok ,  Jawad Khan ,  Richard Coulson

    IPC: G06F3/06 ,  G06F7/72

    Abstract: Technologies for scrambling functions in a column-addressable memory architecture includes a device having a memory and a circuitry. The memory includes a matrix storing individually addressable bit data, and the matrix is formed by rows and columns. The circuitry is to receive a request to perform a write operation of one or more bit values to one of the columns. The circuitry is further to determine a scrambler state at each location of the column, the location corresponding to a respective row and column index. The scrambler state is indicative of a function used to determine a value at the respective column location. Each of the bit values is scrambled as a function of the scrambler state for the respective column location and written thereto.

    Three dimensional circuit systems and methods having memory hierarchies
    10.
    发明授权
    Three dimensional circuit systems and methods having memory hierarchies 有权

    公开(公告)号：US11789641B2

    公开(公告)日：2023-10-17

    申请号：US17349592

    申请日：2021-06-16

    Applicant: Intel Corporation

    Inventor： Scott Weber ,  Jawad Khan ,  Ilya Ganusov ,  Martin Langhammer ,  Matthew Adiletta ,  Terence Magee ,  Albert Fazio ,  Richard Coulson ,  Ravi Gutala ,  Aravind Dasu ,  Mahesh Iyer

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/061 ,  G06F3/0673

    Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

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