公开(公告)号：US5455794A

公开(公告)日：1995-10-03

申请号：US403633

申请日：1995-03-14

申请人： Jahanshir J. Javanifard ,  Albert Fazio ,  Robert E. Larsen ,  James Brennan, Jr. ,  Kerry D. Tedrow

发明人： Jahanshir J. Javanifard ,  Albert Fazio ,  Robert E. Larsen ,  James Brennan, Jr. ,  Kerry D. Tedrow

IPC分类号： G11C16/30 ,  G11C16/06

CPC分类号： G11C16/30

摘要： An integrated circuit which provides an arrangement by which the source of voltage for erasing the flash EEPROM memory array is detected and, if the source is a charge pump, the current provided is held to a constant lower value while, if the source is an external high voltage source, then the current is allowed to flow freely without regulation except by the size of a field effect transistor device in the path from the source of voltage to the memory array. In this manner, the circuitry is adapted to function with either internal or external power sources without paying a performance penalty for either type of operation.

公开(公告)号：US5442586A

公开(公告)日：1995-08-15

申请号：US119425

申请日：1993-09-10

申请人： Jahanshir J. Javanifard ,  Albert Fazio ,  Robert E. Larsen ,  James Brennan, Jr. ,  Kerry D. Tedrow

发明人： Jahanshir J. Javanifard ,  Albert Fazio ,  Robert E. Larsen ,  James Brennan, Jr. ,  Kerry D. Tedrow

IPC分类号： G11C16/30 ,  G11C16/06

CPC分类号： G11C16/30

摘要： An integrated circuit which provides an arrangement by which the source of voltage for erasing the flash EEPROM memory array is detected and, if the source is a charge pump, the current provided is held to a constant lower value while, if the source is an external high voltage source, then the current is allowed to flow freely without regulation except by the size of a field effect transistor device in the path from the source of voltage to the memory array. In this manner, the circuitry is adapted to function with either internal or external power sources without paying a performance penalty for either type of operation.

摘要翻译： 一种集成电路，其提供用于擦除闪存EEPROM存储器阵列的电压源的布置，并且如果源是电荷泵，则所提供的电流被保持为恒定的较低值，而如果源是外部 高电压源，则允许电流自由地流动而不受调节，除了在从电压源到存储器阵列的路径中的场效应晶体管器件的尺寸。 以这种方式，电路适于与内部或外部电源一起工作，而不会对任一类型的操作造成性能损失。

公开(公告)号：US5432469A

公开(公告)日：1995-07-11

申请号：US248419

申请日：1994-05-24

申请人： Kerry D. Tedrow ,  Jahanshir J. Javanifard ,  Cesar Galindo

发明人： Kerry D. Tedrow ,  Jahanshir J. Javanifard ,  Cesar Galindo

IPC分类号： G11C5/14 ,  H02M3/07 ,  H03K5/153 ,  G05F1/10 ,  H03K3/01

CPC分类号： G11C5/145 ,  H02M3/073

摘要： An integrated circuit charge pump circuit including a plurality of stages, each stage including a first N type field effect switching transistor device having source and drain terminals connected in series with the source and drain terminals of all other stages, a second N type field effect control transistor device having drain and source terminals connecting the drain terminal and the gate terminal of the first switching transistor device, and a storage capacitor joined to the source terminal of the first device; a source of voltage to be pumped is connected to the drain terminal of the first device of the first stage. A first series of clock pulses is applied to the gate terminals of the first switching transistor devices in every other stage of the charge pump and to the gate terminals of the second control transistor devices in stages between; and a second series of clock pulses which do not overlap the first series of clock pulses is applied to the gate terminals of the first switching transistor devices in alternate stages of the charge pump and to the gate terminals of the second control transistor devices in stages between the alternate stages. These pulses cause the switching transistor to switch on and off in alternate stages in a manner that the gate terminal goes higher than the drain terminal so that charge is transferred without threshold drop between stages and high current as well as high voltage is pumped to the output terminal.

摘要翻译： 包括多级的集成电路电荷泵电路，每级包括具有与所有其它级的源极和漏极端子串联连接的源极和漏极端子的第一N型场效应开关晶体管器件，第二N型场效应控制 具有连接第一开关晶体管器件的漏极端子和栅极端子的漏极和源极端子的晶体管器件和连接到第一器件的源极端子的存储电容器; 要被泵送的电压源连接到第一级的第一器件的漏极端子。 第一系列时钟脉冲被施加到电荷泵的每隔一级的第一开关晶体管器件的栅极端子和第二控制晶体管器件的栅极端子之间; 并且不与第一系列时钟脉冲重叠的第二系列时钟脉冲在电荷泵的交替级中施加到第一开关晶体管器件的栅极端子，并且在第二组控制晶体管器件的栅极端子之间分阶段地施加 替代阶段。 这些脉冲使得开关晶体管以交替的方式导通和截止，使得栅极端子比漏极端子高，使得电荷在级之间没有阈值下降而被传送，并且高电压被泵送到输出端 终奌站。