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    Display device
    33.
    发明授权
    Display device 有权

    公开(公告)号：US09285911B2

    公开(公告)日：2016-03-15

    申请号：US14152143

    申请日：2014-01-10

    Applicant: Japan Display Inc.

    Inventor： Keiichi Saito ,  Hideyuki Takahashi ,  Takashi Nakamura ,  Satoru Tomita ,  Masahiro Tada ,  Hirotaka Hayashi ,  Takashi Okada ,  Yoshiro Aoki ,  Takanori Tsunashima

    IPC: G06F3/045 ,  G06F3/041 ,  G06F3/044

    Abstract: According to one embodiment, a display device includes a display pixel allocated at a matrix state in a display area, an image-reading device which detects strength of capacitive coupling by a dielectric material coming close to or making contact with the display area, and a control portion which controls each transistor of the image-reading device. The image-reading device includes a detection electrode which forms capacitance between the detection electrode and the dielectric material, a pre-charge gate line, a coupling pulse line, a readout gate line, a pre-charge line and a readout line. These lines supply a signal which drives the image-reading device. The image-reading device further includes a pre-charge transistor, an amplification transistor, a readout transistor, a compensation transistor, and a power-source switching transistor.

    DISPLAY DEVICE
    34.
    发明申请
    DISPLAY DEVICE 有权
    显示设备

    公开(公告)号：US20140333852A1

    公开(公告)日：2014-11-13

    申请号：US14257091

    申请日：2014-04-21

    Applicant: Japan Display Inc.

    Inventor： Miyuki ISHIKAWA ,  Masahiro Tada ,  Takashi Nakamura ,  Yutaka Umeda ,  Hirotaka Hayashi ,  Yoshiro Aoki ,  Takanori Tsunashima

    IPC: G06F3/044 ,  G02F1/1343 ,  G02F1/1333

    CPC classification number: G06F3/044 ,  G02F1/13338 ,  G06F3/0412

    Abstract: According to one embodiment, a display device includes a display panel having a counter substrate, an array substrate and a liquid crystal layer held therebetween, a counter electrode provided on the counter substrate, a pixel electrode arranged on the array substrate in a matrix, a sensor circuit arranged between rows of the plurality of pixel electrodes and configured to read out intensity of capacitive coupling between the sensor circuit and a dielectric, and a counter electrode drive circuit configured to pulsatively drive a common voltage added to the counter electrode during a period of driving the sensor circuit, wherein the sensor circuit comprises a detection electrode configured to form capacitance between the sensor circuit and the dielectric and to form capacitance between the sensor circuit and the counter electrode, and wherein the counter electrode comprises an aperture including at least a portion opposed to the detection electrode.

    Abstract translation: 根据一个实施例，显示装置包括显示面板，其具有对置基板，阵列基板和夹在其间的液晶层，设置在相对基板上的对置电极，以矩阵形式布置在阵列基板上的像素电极， 传感器电路，其布置在所述多个像素电极的行之间并且被配置为读出所述传感器电路和电介质之间的电容耦合的强度;以及对电极驱动电路，被配置为在一段时间期间脉动地驱动添加到所述对电极的公共电压 驱动所述传感器电路，其中所述传感器电路包括被配置为在所述传感器电路和所述电介质之间形成电容并且在所述传感器电路和所述对电极之间形成电容的检测电极，并且其中所述对电极包括孔，所述孔包括至少一部分 与检测电极相对。

    Display apparatus
    35.
    发明授权
    Display apparatus 有权

    公开(公告)号：US12055831B2

    公开(公告)日：2024-08-06

    申请号：US18143624

    申请日：2023-05-05

    Applicant: Japan Display Inc.

    Inventor： Hirotaka Hayashi

    IPC: G02F1/1362 ,  G02F1/1339

    CPC classification number: G02F1/136286 ,  G02F1/1339

    Abstract: Some of a plurality of image signal lines of a display apparatus according to one embodiment includes: a plurality of bypass wiring portions (bypass wirings) arranged in a frame region so as to have both ends being connected to a plurality of extension wiring portions (extension wirings). The plurality of bypass wiring portions of the plurality of image signal lines include: a plurality of second-layer bypass wirings arranged in a second conductive layer; and a plurality of third-layer bypass wirings arranged in a third conductive layer that is different from a first conductive layer and the second conductive layer. Each of an arrangement pitch between the plurality of second-layer bypass wirings and an arrangement pitch between the plurality of third-layer bypass wirings is smaller than an arrangement pitch between the plurality of image signal lines in a display region.

    Semiconductor substrate and display device
    37.
    发明授权
    Semiconductor substrate and display device 有权

    公开(公告)号：US11682732B2

    公开(公告)日：2023-06-20

    申请号：US17184708

    申请日：2021-02-25

    Applicant: Japan Display Inc.

    Inventor： Hirotaka Hayashi ,  Masataka Ikeda

    IPC: H01L29/786 ,  G02F1/167

    CPC classification number: H01L29/7869 ,  G02F1/167

    Abstract: According to one embodiment, a semiconductor layer includes a base, a scanning line disposed over the base, a signal line disposed over the base, a transistor overlapping the scanning line and the signal line and including a first oxide semiconductor layer connected to the signal line, and second oxide semiconductor layers disposed in a same layer as the first oxide semiconductor layer. The second oxide semiconductor layers are disposed around the transistor, and the second oxide semiconductor layers are floating.

    Semiconductor substrate and display device
    38.
    发明授权
    Semiconductor substrate and display device 有权

    公开(公告)号：US11626520B2

    公开(公告)日：2023-04-11

    申请号：US16779680

    申请日：2020-02-03

    Applicant: Japan Display Inc.

    Inventor： Masataka Ikeda ,  Hirotaka Hayashi ,  Hitoshi Tanaka

    IPC: H01L29/786 ,  H01L27/12 ,  G02F1/16766 ,  H01L49/02 ,  G02F1/167

    Abstract: According to one embodiment, a semiconductor substrate includes a first basement, a gate line, a source line, an insulating film, a first pixel electrode, and a first transistor and a second transistor connected parallel at positions between the source line and the first pixel electrode. Each of a first semiconductor layer of the first transistor and a second semiconductor layer of the second transistor includes a first region, a second region, and a channel region. The first semiconductor layer and the second semiconductor layer are in contact with a first surface that is a surface of the insulating film on the source line side. The channel region of each of the first semiconductor layer and the second semiconductor layer wholly overlaps the gate line.

    Display apparatus
    39.
    发明授权
    Display apparatus 有权

    公开(公告)号：US11415852B2

    公开(公告)日：2022-08-16

    申请号：US17464677

    申请日：2021-09-02

    Applicant: Japan Display Inc.

    Inventor： Hirotaka Hayashi

    IPC: G02F1/1362 ,  G02F1/1339

    Abstract: Some of a plurality of image signal lines of a display apparatus according to one embodiment includes: a plurality of bypass wiring portions (bypass wirings) arranged in a frame region so as to have both ends being connected to a plurality of extension wiring portions (extension wirings). The plurality of bypass wiring portions of the plurality of image signal lines include: a plurality of second-layer bypass wirings arranged in a second conductive layer; and a plurality of third-layer bypass wirings arranged in a third conductive layer that is different from a first conductive layer and the second conductive layer. Each of an arrangement pitch between the plurality of second-layer bypass wirings and an arrangement pitch between the plurality of third-layer bypass wirings is smaller than an arrangement pitch between the plurality of image signal lines in a display region.

    Display device
    40.
    发明授权
    Display device 有权

    公开(公告)号：US11183132B2

    公开(公告)日：2021-11-23

    申请号：US17014628

    申请日：2020-09-08

    Applicant: Japan Display Inc.

    Inventor： Masaya Tamaki ,  Tsutomu Harada ,  Hirotaka Hayashi

    IPC: G09G3/36

    Abstract: According to one embodiment, a display device, includes a first pixel line including a first sub-pixel and a second sub-pixel, a second pixel line including a third sub-pixel and a fourth sub-pixel, and a display driver supplying video signals which cause signal polarities of signal lines adjacent to each other to be opposite to each other, without varying the polarities in one frame period, the video signals having the same polarities as each other being written to the respective sub-pixels of the first pixel line, the video signals having the polarities which are the same as each other and opposite to the polarities of the video signals written to the first pixel line, being written to the respective sub-pixels of the second pixel line.

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