公开(公告)号：US20210398598A1

公开(公告)日：2021-12-23

申请号：US17348814

申请日：2021-06-16

Applicant: Kioxia Corporation

Inventor： Taira SHIBUYA ,  Noboru SHIBATA ,  Hironori UCHIKAWA

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/12 ,  G11C16/08 ,  G11C7/06

Abstract: A semiconductor memory device according to an embodiment includes first memory cells, second memory cells, and a controller. A threshold voltage of each of the first memory cells and the second memory cells is included in one of first through sixteenth state. 8-bit data that includes a first through eighth bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell. The controller is configured to: apply in parallel a plurality of types of read voltages to each of the first memory cells and the second memory cells and externally output data confirmed based on first data read from the first memory cells and second data read from the second memory cells.

公开(公告)号：US20200051622A1

公开(公告)日：2020-02-13

申请号：US16654771

申请日：2019-10-16

Applicant: KIOXIA Corporation

Inventor： Weihan WANG ,  Toshifumi HASHIMOTO ,  Noboru SHIBATA

IPC: G11C11/56 ,  G11C16/08 ,  G11C16/32 ,  G06F3/06 ,  G11C16/04

Abstract: A semiconductor memory device includes a first memory cell array including a first memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a second memory cell array including a second memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a first word line electrically connected to a gate of the first memory cell, and a second word line electrically connected to a gate of the second memory cell. In a read operation, at least first, second, and third voltages are applied successively to both the first word line and the second word line to read a first page including the first bit of the first memory cell and a second page including the second bit of the second memory cell.