公开(公告)号：US20060267012A1

公开(公告)日：2006-11-30

申请号：US11498800

申请日：2006-08-04

申请人： Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Il-Jung Kim ,  Kazuhito Tsutsumi ,  Hirotada Kuriyama ,  Yoshiyuki Ishigaki ,  Motomu Ukita ,  Toshiaki Tsutsumi

发明人： Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Il-Jung Kim ,  Kazuhito Tsutsumi ,  Hirotada Kuriyama ,  Yoshiyuki Ishigaki ,  Motomu Ukita ,  Toshiaki Tsutsumi

IPC分类号： H01L31/00

CPC分类号： H01L29/78609 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78624 ,  H01L29/78639

摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.

公开(公告)号：US5789792A

公开(公告)日：1998-08-04

申请号：US788732

申请日：1997-01-23

申请人： Toshiaki Tsutsumi

发明人： Toshiaki Tsutsumi

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/41

CPC分类号： H01L21/76229

摘要： A structure includes an element isolating region for isolating a transistor formation region having an MOS transistor from other element formation region. Two or more trenches is formed at a semiconductor substrate in the element isolation region. An isolating and insulating layer filling the trench and protruded above the main surface of the semiconductor substrate has a side surface continuous with a side surface of the trench. Insulating layers and layered on the surface of the semiconductor substrate is located between the trenches. The insulating layer has the upper surface at the substantially same level as the upper surface of an isolating and insulating layer. This structure suppresses increase in a parasitic capacitance of a gate electrode, and allows a fast operation without difficulty.

摘要翻译： 一种结构包括用于将具有MOS晶体管的晶体管形成区域与其它元件形成区域隔离的元件隔离区域。 在元件隔离区域中的半导体衬底处形成两个或更多个沟槽。 填充沟槽并突出在半导体衬底的主表面上方的隔离和绝缘层具有与沟槽的侧表面连续的侧表面。 在半导体衬底的表面上分层的绝缘层位于沟槽之间。 绝缘层的上表面与隔离层和绝缘层的上表面基本相同。 这种结构抑制了栅电极的寄生电容的增加，并且难以快速操作。