Semiconductor memory device, controller, and read/write control method thereof
    31.
    发明授权
    Semiconductor memory device, controller, and read/write control method thereof 有权
    半导体存储器件,控制器及其读/写控制方法

    公开(公告)号:US07203105B2

    公开(公告)日:2007-04-10

    申请号:US10553974

    申请日:2004-10-13

    IPC分类号: G11C7/00

    CPC分类号: G06F12/06 G06F2212/2022

    摘要: A controller 102 and four flash memories F0 to F3 are connected by twos to two memory buses, and each flash memory is divided into two regions of substantially the same size to form a first half and a last half regions. In a four-memory configuration, a consecutive logical address specified by a host apparatus is divided into a predetermined size, and a write operation is performed in a format that repeatedly circulates through F0, F1, F2, F3 in this order. In a two-memory configuration, the write operation is performed in a format that repeatedly circulates through F00, F10, F01, F11. Thus, a controller processing is made common regardless of the number of flash memories connected to the controller.

    摘要翻译: 控制器102和四个闪速存储器F 0至F 3通过两个连接到两个存储器总线,并且每个闪速存储器被划分为大致相同大小的两个区域,以形成前半部分和后半个区域。 在四存储器配置中,由主机设备指定的连续逻辑地址被划分为预定大小,并以按顺序重复循环的格式执行写入操作。 。 在双存储器配置中,写入操作以通过F 00,F 10,F 01,F 11重复循环的格式执行。 因此,与控制器连接的闪存数量无关,控制器处理是常见的。

    Semiconductor memory device, memory controller and data recording method
    32.
    发明申请
    Semiconductor memory device, memory controller and data recording method 审中-公开
    半导体存储器件,存储器控制器和数据记录方法

    公开(公告)号:US20050204115A1

    公开(公告)日:2005-09-15

    申请号:US11043411

    申请日:2005-01-27

    IPC分类号: G06F12/08

    CPC分类号: G06F12/0246

    摘要: A read/write memory 109 is provided with a memory controller 110 so as to store address management information temporarily. A non-volatile memory access unit 106 writes user data on a non-volatile memory 111 according to a write instruction. When the user data is rewritten, an address management information controller 105 causes a physical block, which is an object to which the address management information 108 is rewritten, to be a to-be-invalid block. After completion of a series of writing process, the to-be-invalid block is turned into an invalid block and the address management information in the read/write memory 109 is rewritten on the non-volatile memory 111.

    摘要翻译: 读/写存储器109设置有存储器控制器110,以临时存储地址管理信息。 非易失性存储器访问单元106根据写入指令将用户数据写入非易失性存储器111。 当用户数据被重写时,地址管理信息控制器105使作为地址管理信息108被重写的对象的物理块成为无效块。 在完成一系列写入处理之后,将无效块变成无效块,并且读/写存储器109中的地址管理信息被重写在非易失性存储器111上。

    Semiconductor memory device, controller, and read/write control method thereof
    33.
    发明授权
    Semiconductor memory device, controller, and read/write control method thereof 有权
    半导体存储器件,控制器及其读/写控制方法

    公开(公告)号:US07633817B2

    公开(公告)日:2009-12-15

    申请号:US11712387

    申请日:2007-03-01

    IPC分类号: G11C7/00

    CPC分类号: G06F12/06 G06F2212/2022

    摘要: A controller 102 and four flash memories F0 to F3 are connected by twos to two memory buses, and each flash memory is divided into two regions of substantially the same size to form a first half and a last half regions. In a four-memory configuration, a consecutive logical address specified by a host apparatus is divided into a predetermined size, and a write operation is performed in a format that repeatedly circulates through F0, F1, F2, F3 in this order. In a two-memory configuration, the write operation is performed in a format that repeatedly circulates through F00, F10, F01, F11. Thus, a controller processing is made common regardless of the number of flash memories connected to the controller.

    摘要翻译: 控制器102和四个闪速存储器F0至F3通过两个连接到两个存储器总线,并且每个闪速存储器被划分为大致相同大小的两个区域,以形成前半部分和后半个区域。 在四存储器配置中,由主机设备指定的连续逻辑地址被划分为预定大小,并且以按顺序重复循环通过F0,F1,F2,F3的格式执行写入操作。 在双存储器配置中,写入操作以通过F00,F10,F01,F11重复循环的格式执行。 因此,无论连接到控制器的闪存数量如何,控制器处理都是常见的。

    Memory card, data processor, memory card control method and memory card setting
    34.
    发明授权
    Memory card, data processor, memory card control method and memory card setting 失效
    存储卡,数据处理器,存储卡控制方式和存储卡设置

    公开(公告)号:US07624298B2

    公开(公告)日:2009-11-24

    申请号:US10597650

    申请日:2005-02-02

    IPC分类号: G06F11/00

    摘要: A memory card (1) includes a host interface (2) that transmits and receives a command and data to and from the data processor (50), a nonvolatile memory (7) that stores data, a controller (3) that controls the operation of the memory card, and a storage section (32) that stores specified management information. The management information includes retry setting information which specifies whether a retry function is executed or not when an error occurs during an operation of writing data to the nonvolatile memory. The controller (3) refers to the retry setting information in the data writing operation, and controls the data writing operation so as to disable the retry function in the event of an error in the data writing operation, when the retry setting information indicates disabling of the retry function or to enable the retry function in the event of an error in the data writing operation, when the retry setting information indicates enabling of the retry function.

    摘要翻译: 存储卡(1)包括向数据处理器(50)发送和接收命令和数据的主机接口(2),存储数据的非易失性存储器(7),控制操作的控制器(3) 以及存储指定的管理信息的存储部(32)。 管理信息包括重试设置信息,其在向非易失性存储器写入数据的操作期间发生错误时指定是否执行重试功能。 控制器(3)参考数据写入操作中的重试设置信息,并且当重试设置信息指示禁用时,控制数据写入操作以便在数据写入操作中发生错误的情况下禁用重试功能 重试功能,或者当重试设置信息指示重试功能的启用时,在数据写入操作中发生错误的情况下启用重试功能。

    Memory card, data processor,memory card control method and memory card setting
    36.
    发明申请
    Memory card, data processor,memory card control method and memory card setting 失效
    存储卡,数据处理器,存储卡控制方式和存储卡设置

    公开(公告)号:US20070186040A1

    公开(公告)日:2007-08-09

    申请号:US10597650

    申请日:2005-02-02

    IPC分类号: G06F12/00

    摘要: A memory card (1) includes a host interface (2) that transmits and receives a command and data to and from the data processor (50), a nonvolatile memory (7) that stores data, a controller (3) that controls the operation of the memory card, and a storage section (32) that stores specified management information. The management information includes retry setting information which specifies whether a retry function is executed or not when an error occurs during an operation of writing data to the nonvolatile memory. The controller (3) refers to the retry setting information in the data writing operation, and controls the data writing operation so as to disable the retry function in the event of an error in the data writing operation, when the retry setting information indicates disabling of the retry function or to enable the retry function in the event of an error in the data writing operation, when the retry setting information indicates enabling of the retry function.

    摘要翻译: 存储卡(1)包括向数据处理器(50)发送和接收命令和数据的主机接口(2),存储数据的非易失性存储器(7),控制操作的控制器(3) 以及存储指定的管理信息的存储部(32)。 管理信息包括重试设置信息,其在向非易失性存储器写入数据的操作期间发生错误时指定是否执行重试功能。 控制器(3)参考数据写入操作中的重试设置信息,并且当重试设置信息指示禁用时,控制数据写入操作以便在数据写入操作中发生错误的情况下禁用重试功能 重试功能,或者当重试设置信息指示重试功能的启用时,在数据写入操作中发生错误的情况下启用重试功能。