公开(公告)号：US5621860A

公开(公告)日：1997-04-15

申请号：US257775

申请日：1994-06-09

申请人： Biagio Russo ,  Claudio Luzzi ,  Rinaldo Poluzzi

发明人： Biagio Russo ,  Claudio Luzzi ,  Rinaldo Poluzzi

IPC分类号： G06F9/44 ,  G05B13/02 ,  G06F1/035 ,  G06N7/02 ,  G06N7/04 ,  G06G7/00

CPC分类号： G06N7/04 ,  G05B13/0275 ,  G06F1/035 ,  Y10S706/90

摘要： A method for loading the memory of an electronic controller operating using fuzzy logic, whereby predetermined membership functions of logic variables, defined within a universe of discourse sampled in a finite number of points, are subjected to inference operations basically configured as IF/THEN rules with at least one front preposition and at least one rear implication. The controller includes a central control unit provided with a memory section for storing predetermined values of the membership functions which appear in the front or IF part of the fuzzy rules and have a predetermined degree of truth or membership. This method provides for storing the memory section the only values of those membership functions that have a value of the degree of membership other than zero at the points of the universe of discourse.

摘要翻译： 一种用于加载使用模糊逻辑操作的电子控制器的存储器的方法，由此在有限数量的点中采样的话语范围内定义的逻辑变量的预定隶属度函数经受基本上被配置为IF / THEN规则的推理操作， 至少一个前置介面和至少一个后方暗示。 该控制器包括中央控制单元，该中央控制单元设置有存储部分，用于存储出现在模糊规则的正面或中间部分中并具有预定程度的真值或隶属度的隶属函数的预定值。 这种方法提供了存储器部分的唯一值，它们是在话语世界的点处具有不属于零的隶属度的值的那些隶属函数的值。

公开(公告)号：US5574826A

公开(公告)日：1996-11-12

申请号：US257340

申请日：1994-06-09

申请人： Biagio Russo ,  Claudio Luzzi ,  Rinaldo Poluzzi

发明人： Biagio Russo ,  Claudio Luzzi ,  Rinaldo Poluzzi

IPC分类号： G06F9/44 ,  G05B13/02 ,  G06F1/035 ,  G06N7/02 ,  G06N7/04 ,  G06G7/00 ,  G06F17/00

CPC分类号： G06F1/035 ,  G05B13/0275 ,  G06N7/04 ,  Y10S706/90

摘要： A method for setting up the memory of an electronic controller operates using fuzzy logic, whereby predetermined membership functions f(m) of logic variables M, defined within a universe of discourse sampled in a finite number of points m, are subjected to inference operations basically configured by IF/THEN rules with at least one front preposition and at least one rear implication. The controller includes a central control unit provided with a memory section for storing predetermined values of the membership functions f(m) which appear in the front or IF part of the fuzzy rules and have a predetermined degree of truth or membership. This method provides for storing into the memory section only the values of those membership functions f(m) which have a value of the degree of membership other than zero at the points m of the universe of discourse.

摘要翻译： 用于设置电子控制器的存储器的方法使用模糊逻辑运行，由此在有限数量的点m中采样的话语范围内定义的逻辑变量M的预定隶属函数f（m）基本上受到推理操作 由IF / THEN规则配置，具有至少一个前置介质和至少一个后置隐含。 该控制器包括一个中央控制单元，该中央控制单元设置有存储部分，用于存储出现在模糊规则的正面或中间部分中并具有预定程度的真值或隶属度的隶属函数f（m）的预定值。 该方法仅在存储器部分中存储那些隶属度函数f（m）的值，它们具有在话语世界的点m处的隶属程度不为零的值。

公开(公告)号：USRE37440E1

公开(公告)日：2001-11-06

申请号：US08021489

申请日：1993-02-23

申请人： Franco Cavallotti ,  Alessandro Cremonesi ,  Rinaldo Poluzzi

发明人： Franco Cavallotti ,  Alessandro Cremonesi ,  Rinaldo Poluzzi

IPC分类号： G06F1710

CPC分类号： H03H17/0294 ,  H03H17/0607

摘要： The filter includes an arithmetical chain of parallel adders alternated with delay elements, and a memory constituted by lines of one-bit cells. Each line is addressable by a decoder controlled by a digital signal to be filtered; each line of memory contains side by side values which correspond to the partial products of successive impulse-response coefficients for a value equal to the line address. The memory additionally includes a number of read amplifiers. The number of read amplifiers is equal to the number of cells of one line in order to read the bits of the addressed. The outputs of the amplifiers are connected to respective parallel inputs of the adders of the arithmetical chain. Each memory line contains these values in two's-complement binary form in words which decrease in length by one bit for each increment of 2 in the characteristic of the coefficients, starting from the one of lowest characteristic. The output of each read amplifier corresponding to the most significant bit of each value is connected to the corresponding input bit line of the associated adder and to all the other most significant input bit lines.

摘要翻译： 滤波器包括与延迟元件交替的并行加法器的算术链，以及由一位单元的行构成的存储器。 每行可由被要滤波的数字信号控制的解码器寻址; 存储器的每一行包含对应于等于行地址的值的连续脉冲响应系数的部分乘积的并行值。 存储器还包括多个读取放大器。 读取放大器的数量等于一行的单元数，以便读取寻址的位。 放大器的输出端连接到算术链的加法器的相应并行输入端。 每个存储线包含两个补码二进制形式的这些值，它们以从最低特性之一开始的系数特性中的每个增量2减少一位的长度减去一位。 与每个值的最高有效位相对应的每个读取放大器的输出连接到相关联的加法器的相应输入位线和所有其他最重要的输入位线。

公开(公告)号：US5103416A

公开(公告)日：1992-04-07

申请号：US439792

申请日：1989-11-21

申请人： Franco Cavallotti ,  Alessandro Cremonesi ,  Rinaldo Poluzzi

发明人： Franco Cavallotti ,  Alessandro Cremonesi ,  Rinaldo Poluzzi

IPC分类号： H03H17/02 ,  H03H17/06

CPC分类号： H03H17/0607 ,  H03H17/02 ,  H03H17/0294 ,  H03H17/06 ,  H03H2017/0692

摘要： The digital filter includes a plurality of parallel adders, each whereof has a first input, a second input and an output; the parallel output of each adder is connected to the first input of the successive adder across a respective delay element. The second input of each adder is connected in parallel to the output of one of a plurality of memory banks, each whereof comprises a plurality of addressable memory cells, the addressing inputs whereof can be driven by a sampled digital signal to be filtered, and the memory cells of each bank contain a digital value which is equal to the product of a preset coefficient by the address of the cell itself.