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公开(公告)号：US12087267B2
公开(公告)日：2024-09-10
申请号：US17978900
申请日：2022-11-01
申请人： Jonathan Abel
发明人： Jonathan Abel
CPC分类号： G10K15/12 , G01R23/00 , G10H1/366 , G10H5/007 , G10H5/02 , G10H2210/281 , G10H2210/311 , G10H2210/325 , G10H2250/111 , H03H17/02 , H04S7/305
摘要： The implementation of modal processors, which involve the parallel combination resonant filters, may be costly for applications such as artificial reverberation that can require thousands of modes. In one embodiment, the input signal is decomposed into a plurality of subbands, the outputs of which are downsampled. In each downsampled band, resonant filters are applied at the downsampled sampling rate, and their output is upsampled and filtered to form the band output. In these and other embodiments, a feature of responses of the mode filters have been optimized to minimize an aspect of a residual error after a point in time.
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公开(公告)号：US20240220779A1
公开(公告)日：2024-07-04
申请号：US18527063
申请日：2023-12-01
发明人： Vignesh Vivekraja , Tomonari Tohara , Reza Tusi , Abuduwaili Tuoheti , Javid Jaffari , Vlad Fruchter , David Vakrat , Ohad Meitav
IPC分类号： G06N3/0464 , G06F7/544 , G06F17/15 , H03H17/02
CPC分类号： G06N3/0464 , G06F7/5443 , G06F17/153 , H03H17/02
摘要： In one embodiment, a system comprising a processor and a non-transitory memory coupled to the processor comprising instructions executable by the processor. The processor, comprising an internal memory; a Multiply-Accumulate (MAC) array; a first vector register array; a second vector register array; and a third vector register array, is operable when executing instructions to transfer weights for M filters and an input activation tensor from an external memory to the internal memory, insert paddings to the input activation tensor in the internal memory based on first configuration parameters, configure the MAC array to a required shape based on second configuration parameters for convolution operations between the input activation tensor and the M filters, and calculate a row of the output activation tensor by performing the convolution operations on corresponding R rows of the input activation tensor with the M filters, wherein R is a filter height.
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公开(公告)号：US20240195425A1
公开(公告)日：2024-06-13
申请号：US18582728
申请日：2024-02-21
发明人： Fahim ur RAHMAN , Jinuk SHIN
CPC分类号： H03L7/10 , H03H17/02 , H03L7/0812 , H03L7/093 , H03H2017/0081
摘要： An integrated circuit (IC) features a delay-locked loop (DLL) with a DLL signal input. The DLL comprises a delay line with multiple delay stages, a gater with clock input, and a phase-frequency detector (PFD). The delay line's signal input is linked to the DLL signal input, while the gater's inputs are connected to phase outputs of the delay line. The gater's clock input is tied to the DLL signal input, and its outputs feed into the PFD inputs. The PFD generates outputs that are used by a loop filter to control the speed of the delay line.
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公开(公告)号：US11916559B2
公开(公告)日：2024-02-27
申请号：US18090748
申请日：2022-12-29
发明人： Fahim Ur Rahman , Jinuk Shin
CPC分类号： H03L7/10 , H03H17/02 , H03L7/0812 , H03L7/093 , H03H2017/0081
摘要： A DLL includes a delay line with two phase outputs, a gater coupled with the delay line phase outputs, a PFD coupled with gater outputs, a PD coupled with PFD outputs, a retimer coupled with PD outputs, and a loop filter with inputs coupled with the retimer and a speed control output coupled with the delay line. The gater passes signals on its two inputs to its two outputs, apart from a first pulse on its first input. The PD determines if the second gated signal leads or lags the first gated signal. The retimer retimes PD output signals to be aligned with a delay line input signal. The loop filter uses the retimed PD output signals to determine if the delay line should delay more or delay less, and outputs a speed control signal to control the delay line speed.
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公开(公告)号：US11823698B2
公开(公告)日：2023-11-21
申请号：US17384292
申请日：2021-07-23
IPC分类号： G10L21/0272 , H04S7/00 , H04R1/40 , H04R3/00 , H03H17/02 , G06F3/0484 , H04N5/262
CPC分类号： G10L21/0272 , G06F3/0484 , H03H17/02 , H04N5/2628 , H04R1/406 , H04R3/005 , H04S7/30 , H04R2430/03 , H04S2400/15
摘要： A method of cropping a portion of an audio signal captured from a plurality of spatially separated audio sources in a scene, the method comprising: capturing the audio signal with one or more recording devices; separating the audio signal into a plurality of components each associated with one or more of the plurality of audio sources; selecting a spatial region in the scene; determining which of the plurality of components are associated with an audio source positioned outside of the selected spatial region; and cropping the plurality of components associated with an audio source positioned outside of the selected spatial region out of the audio signal.
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公开(公告)号：US11799453B2
公开(公告)日：2023-10-24
申请号：US17698033
申请日：2022-03-18
CPC分类号： H03H17/02 , H03F3/183 , H04R3/04 , H04R17/00 , H04R29/001 , H03F2200/03 , H04R2201/003
摘要： A circuit for driving a capacitive load includes an amplifier for driving the load based on an input signal, the amplifier comprising at least a boost converter, a dynamic model configured to track a capacitance of the load and a voltage of the source for powering at least parts of the circuit, an adaptive filter, configured to filter the input signal based on an output of the dynamic model.
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公开(公告)号：US11698638B2
公开(公告)日：2023-07-11
申请号：US17708886
申请日：2022-03-30
申请人： Peyman Yadmellat , Mohsen Rohani
发明人： Peyman Yadmellat , Mohsen Rohani
CPC分类号： G05D1/0212 , G07C5/02 , G05D1/0088 , H03H17/02
摘要： A processor-implemented method and system for determining a predictive occupancy grid map (OGM) for an autonomous vehicle are disclosed. The method includes: receiving a set of OGMs including a current predicted OGM and one or more future predicted OGMs, the current OGM associated with a current timestamp and each future predicted OGM associated with a future timestamp; generating a weight map associated with the current timestamp based on one or more kinodynamic parameters of the vehicle at the current time stamp, and one or more weight map associated with a future timestamp; generating a set of filtered predicted OGMs by filtering the current predicted OGM with the weight map associated the current timestamp and filtering each respective future predicted OGM associated with a future timestamp with the weight map associated with the respective future timestamp; and sending a single predicted OGM to a trajectory generator.
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公开(公告)号：US09929721B2
公开(公告)日：2018-03-27
申请号：US15291187
申请日：2016-10-12
发明人： Curt Karnstedt
摘要： Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for detecting characteristics of an input signal. One aspect includes a first finite impulse response (FIR) filter, a second FIR filter, and a controller coupled with the first and second FIR filters. The first FIR filter receives an input signal and a first reference signal. The first FIR filter filters the first reference signal to generate a first sinusoidal signal and mixes the first sinusoidal signal and the input signal to generate a first mixed signal. The second FIR filter receives the input signal and a second reference signal. The second FIR filter filters the second reference signal to generate a second sinusoidal signal and mixes the second sinusoidal signal and the input signal to generate a second mixed signal. The controller determines characteristics of the input signal based on the first and second mixed signals.
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公开(公告)号：US20170315748A1
公开(公告)日：2017-11-02
申请号：US15531415
申请日：2015-11-30
发明人： Dongmei Lei
CPC分类号： G06F3/0638 , G06F3/0604 , G06F3/0656 , G06F3/0673 , H03H17/02 , H03H17/0263 , H04N19/42 , H04N19/80
摘要： A median filter device is provided with a reordered circuit, a comparison circuit and a data refresh circuit on the basis of the conventional data buffer circuit and data register circuit. The reorder circuit re-sorts the signal data stored in the data buffer circuit in a preceding clock cycle according to their numerical values. The comparison circuit compares the new signal datum entered in the current clock cycle with the signal data already stored to generate a median. The data refresh circuit updates the signal codes stored in the data register circuit with the signal codes corresponding to the new signal data, for calculation of the median in a following clock cycle. The length of the data buffer circuit and data register circuit can be reduced from N signal data to N-1 signal data, which achieves less data storage capacity, smaller circuit area, easier data processing and higher operation efficiency.
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公开(公告)号：US20170111029A1
公开(公告)日：2017-04-20
申请号：US15291187
申请日：2016-10-12
发明人： Curt Karnstedt
摘要： Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for detecting characteristics of an input signal. One aspect includes a first finite input response (FIR) filter, a second FIR filter, and a controller coupled with the first and second FIR filters. The first FIR filter receives an input signal and a first reference signal. The first FIR filter filters the first reference signal to generate a first sinusoidal signal and mixes the first sinusoidal signal and the input signal to generate a first mixed signal. The second FIR filter receives the input signal and a second reference signal. The second FIR filter filters the second reference signal to generate a second sinusoidal signal and mixes the second sinusoidal signal and the input signal to generate a second mixed signal. The controller determines characteristics of the input signal based on the first and second mixed signals.
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