公开(公告)号：US5043990A

公开(公告)日：1991-08-27

申请号：US279034

申请日：1988-12-02

申请人： Toshio Doi ,  Takehisa Hayashi ,  Kenichi Ishibashi

发明人： Toshio Doi ,  Takehisa Hayashi ,  Kenichi Ishibashi

IPC分类号： G06F7/00 ,  G06F11/10 ,  G06F11/16

CPC分类号： G06F11/1641 ,  G06F11/10 ,  G06F7/57

摘要： A semiconductor integrated circuit device is provided which includes a logic circuit utilizing an error detection code. The device has a first circuit train including a series connection of plural stages of operation circuits for receiving input data, performing predetermined operations while the input data propagates through the operation circuits and providing output data; a second circuit train including a series connection of plural stages of error detection code correction circuits for receiving error detection code input corresponding to the input data, applying corrections to the error detection code in correspondence to the operations in the operation circuits in the first circuit train, and outputting an error detection code corresponding to the output data; and at least one error detection circuit for performing a comparison and check of the output of the operation circuit in the first circuit train and the output of a corresponding error detection code correction circuit in the second circuit train. Also, the semiconductor integrated circuit device of this invention comprises a logic circuit incorporating therein an error detection function by doubling the circuits which comprise a logic circuit using the error detection code, doubled operation circuits having the same function and inputted with the same signal, and a comparison circuit for mutually comparing the outputs of the doubled operation circuits.

摘要翻译： 提供一种半导体集成电路器件，其包括利用错误检测码的逻辑电路。 该装置具有第一电路列，其包括用于接收输入数据的多级操作电路的串联连接，当输入数据通过操作电路传播并提供输出数据时执行预定操作; 包括多级错误检测码校正电路的串联连接的第二电路列，用于接收对应于输入数据的错误检测码输入，对应于第一电路列中的操作电路中的操作对错误检测码进行校正 并且输出与所述输出数据相对应的错误检测码; 以及至少一个误差检测电路，用于对第一电路列中的运算电路的输出和第二电路列中相应的检错码校正电路的输出进行比较和检查。 此外，本发明的半导体集成电路器件包括一个逻辑电路，其中结合有误差检测功能，通过使用误差检测码将包括逻辑电路的电路加倍，具有相同功能的双倍运算电路并输入相同的信号，以及 比较电路，用于相互比较双重运算电路的输出。

公开(公告)号：US4849660A

公开(公告)日：1989-07-18

申请号：US201961

申请日：1988-06-03

申请人： Takehisa Hayashi ,  Kenichi Ishibashi ,  Toshio Doi

发明人： Takehisa Hayashi ,  Kenichi Ishibashi ,  Toshio Doi

IPC分类号： H03K19/0175 ,  H03K19/0944

CPC分类号： H03K19/017518 ,  H03K19/09448

摘要： An output interface circuit comprises a CMOS circuit including a pair of complementary MOS transistors and receiving an input signal at the gates of the paired MOS transistors, a bipolar transistor having its base connected to the output of the CMOS circuit and its emitter from which an output signal is delivered, and a control circuit connected between the paired MOS transistors and operable, upon the fall of the output signal, to cut off a current flowing through any one of the paired MOS transistors so as to control the low level at the output of the CMOS circuit such that the low level does not fall before a potential level by which the low level of the output signal is permitted to be at a desirable predetermined potential level. Specifically, the CMOS circuit includes a pair of complementary MOS transistors comprised of a P-type MOS transistor and an N-type MOS transistor and receives an input signal of CMOS level to operate in inverter fashion. The bipolar transistor connected to the output of the CMOS circuit operates as an emitter follower to deliver an output signal of ECL level. Upon the fall of the output signal, the control circuit operates to cut off a current flowing through the N-type MOS transistor so as to control the low level at the output of the CMOS circuit such that the low level does not fall below a level which is about 0.5 to 0.8 volts higher than the low level of the output signal (ECL level) of the bipolar transistor.

摘要翻译： 输出接口电路包括CMOS电路，其包括一对互补MOS晶体管，并在所述成对MOS晶体管的栅极处接收输入信号;双极晶体管，其基极连接到CMOS电路的输出端及其发射极， 信号被输送，以及控制电路，连接在成对的MOS晶体管之间，并且在输出信号的下降时可以切断流过成对的MOS晶体管中的任何一个的电流，以便控制在输出端的低电平 CMOS电路使得低电平不会落在允许输出信号的低电平处于期望的预定电位电平的电位电平之前。 具体地说，CMOS电路包括由P型MOS晶体管和N型MOS晶体管组成的一对互补MOS晶体管，并接收CMOS电平的输入信号以逆变器方式工作。 连接到CMOS电路的输出的双极晶体管用作射极跟随器来传送ECL电平的输出信号。 在输出信号的下降时，控制电路工作以切断流过N型MOS晶体管的电流，以便控制CMOS电路的输出处的低电平，使得低电平不低于电平 其比双极晶体管的输出信号（ECL电平）的低电平高约0.5至0.8伏。

公开(公告)号：US4159378A

公开(公告)日：1979-06-26

申请号：US884525

申请日：1978-03-08

申请人： Kenichi Ishibashi ,  Susumu Ishiguro ,  Reiko Komaki

发明人： Kenichi Ishibashi ,  Susumu Ishiguro ,  Reiko Komaki

IPC分类号： C07D405/04 ,  C07D239/54

CPC分类号： C07D405/04

摘要： A novel and very elegant method is proposed for the preparation of N.sub.1 -(2-tetrahydrofuryl)-5-substituted or -unsubstituted uracil, especially, N.sub.1 -(2-tetrahydrofuryl)-5-fluorouracil, by the reaction of the corresponding 5-substituted uracil compound with 2,3-dihydrofuran. The reaction is performed in the presence of a chlorosilane compound, e.g. dimethyldichlorosilane, and a catalytic amount of an organic amine compound and can proceed very rapidly without disadvantageous side reactions to give the objective compound with high purity in a high yield.

摘要翻译： 提出了一种新颖而优雅的方法，用于制备N1-（2-四氢呋喃基）-5-取代或取代的尿嘧啶，特别是N1-（2-四氢呋喃基）-5-氟尿嘧啶，通过相应的5- 取代的尿嘧啶化合物与2,3-二氢呋喃。 反应在氯硅烷化合物的存在下进行，例如 二甲基二氯硅烷和催化量的有机胺化合物，并且可以非常快速地进行而没有不利的副反应，以高产率得到高纯度的目标化合物。