公开(公告)号：US20220368349A1

公开(公告)日：2022-11-17

申请号：US17302226

申请日：2021-04-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Jaime Cummins

IPC: H03M13/01 ,  H03M13/13 ,  H03M13/11 ,  G06N3/08 ,  G06N3/04

Abstract: Examples described herein utilize multi-layer neural networks, such as multi-layer recurrent neural networks to estimate message probability compute data based on encoded data (e.g., data encoded using one or more encoding techniques). The neural networks and/or recurrent neural networks may have nonlinear mapping and distributed processing capabilities which may be advantageous in many systems employing a neural network or recurrent neural network to estimate message probability compute data for a message probability compute (MPC) decoder. In this manner, neural networks or recurrent neural networks described herein may be used to implement aspects of error correction coding (ECC) decoders, e.g., an MPC decoder that iteratively decodes encoded data.

公开(公告)号：US20220254400A1

公开(公告)日：2022-08-11

申请号：US17729830

申请日：2022-04-26

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Jaime Cummins

IPC: G11C11/34 ,  G06F9/30 ,  G06F9/50 ,  H04N5/232 ,  G06N3/063 ,  G06F9/38

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to execute instructions with matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; a first interface to a memory controller of a Central Processing Unit; and a second interface to an image generator, such as a camera. While the Deep Learning Accelerator is using the random access memory to process current input to the Artificial Neural Network in generating current output from the Artificial Neural Network, the Deep Learning Accelerator may concurrently load next input from the camera into the random access memory; and at the same time, the Central Processing Unit may concurrently retrieve prior output from the random access memory.

公开(公告)号：US20220147811A1

公开(公告)日：2022-05-12

申请号：US17092038

申请日：2020-11-06

Applicant: Micron Technology, Inc.

Inventor： Jaime Cummins ,  Marko Vitez ,  Eugenio Culurciello ,  Andre Xian Ming Chang ,  Aliasger Tayeb Zaidy

IPC: G06N3/08 ,  G06N3/04 ,  G06F8/41 ,  G11C11/54

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory (RAM). A compiler can identify a plurality of portions of an artificial neural network for implementation on a plurality of such integrated circuit devices respectively. The compiler converts a description of the artificial neural network into a plurality of compiler outputs executable on the plurality of devices to generate an output of the artificial neural network response to an input to the artificial neural network. Intermediate results are communicated among the devices in generating the output of the artificial neural network.

公开(公告)号：US11206050B2

公开(公告)日：2021-12-21

申请号：US15890275

申请日：2018-02-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

IPC: H04W72/08 ,  H04B1/04 ,  H04L5/14 ,  H04B1/525

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of full duplex compensation with a self-interference noise calculator that compensates for the self-interference noise generated by power amplifiers at harmonic frequencies of a respective wireless receiver. The self-interference noise calculator may be coupled to antennas of a wireless device and configured to generate the adjusted signals that compensate self-interference. The self-interference noise calculator may include a network of processing elements configured to combine transmission signals into sets of intermediate results. Each set of intermediate results may be summed in the self-interference noise calculator to generate a corresponding adjusted signal. The adjusted signal is receivable by a corresponding wireless receiver to compensate for the self-interference noise generated by a wireless transmitter transmitting on the same or different frequency band as the wireless receiver is receiving.

公开(公告)号：US11201646B2

公开(公告)日：2021-12-14

申请号：US16844178

申请日：2020-04-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Tamara Schmitz ,  Jeremy Chritz ,  Jaime Cummins

IPC: H04B7/0456 ,  H04B7/08 ,  G06F17/15 ,  H04B7/0413 ,  H04W84/00

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of an autocorrelation calculator. An electronic device including an autocorrelation calculator may be configured to calculate an autocorrelation matrix including an autocorrelation of symbols indicative of a first radio frequency (“RF”) signal and a second RF signal. The electronic device may calculate the autocorrelation matrix based on a stored autocorrelation matrix and the autocorrelation of symbols indicative of the first RF signal and symbols indicative of the second RF signal. The stored autocorrelation matrix may represent another received signal at a different time period than a time period of the first and second RF signals. Examples of the systems and methods may facilitate the processing of data for wireless and may utilize less memory space than a device than a scheme that stores and calculates autocorrelation from a large dataset computed from various time points.

公开(公告)号：US20210328631A1

公开(公告)日：2021-10-21

申请号：US17362672

申请日：2021-06-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

IPC: H04B7/0413 ,  G06N3/08 ,  G06N3/04

Abstract: Examples described herein include systems and methods, including wireless devices and systems with neuron calculators that may perform one or more functionalities of a wireless transceiver. The neuron calculator calculates output signals that may be implemented, for example, using accumulation units that sum the multiplicative processing results of ordered sets from ordered neurons with connection weights for each connection between an ordered neuron and outputs of the neuron calculator. The ordered sets may be a combination of some input signals, with the number of signals determined by an order of the neuron. Accordingly, a kth-order neuron may include an ordered set comprising product values of k input signals, where the input signals are selected from a set of k-combinations with repetition. As an example in a wireless transceiver, the neuron calculator may perform channel estimation as a channel estimation processing component of the receiver portion of a wireless transceiver.

公开(公告)号：US20210319822A1

公开(公告)日：2021-10-14

申请号：US16844993

申请日：2020-04-09

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Jaime Cummins

IPC: G11C11/34 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06N3/063

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to execute instructions with matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; a first interface to a memory controller of a Central Processing Unit; and a second interface to a direct memory access controller. While the Deep Learning Accelerator is using the random access memory to process current input to the Artificial Neural Network in generating current output from the Artificial Neural Network, the direct memory access controller may concurrently load next input into the random access memory; and at the same time, the Central Processing Unit may concurrently retrieve prior output from the random access memory.

公开(公告)号：US20210318871A1

公开(公告)日：2021-10-14

申请号：US16845010

申请日：2020-04-09

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Jaime Cummins

IPC: G06F9/30 ,  G06F9/50 ,  G06F9/38 ,  G06N3/063 ,  A61B5/00 ,  H04L29/08

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An edge server may be configured on a local area network to receive sensor data of a person, such as a patient in a hospital or care center. The edge server may be implemented using an integrated circuit device having: a Deep Learning Accelerator configured to execute instructions with matrix operands; and random access memory configured to store first instructions of an Artificial Neural Network executable by the Deep Learning Accelerator and second instructions of a server application executable by a Central Processing Unit. An output of the Artificial Neural Network with the sensor data as input may identify a condition of the person, based on which the server application generates an alert, causing a central server to request intervention of the detected or predicted condition for the person.

公开(公告)号：US20210165732A1

公开(公告)日：2021-06-03

申请号：US17150675

申请日：2021-01-15

Applicant: Micron Technology, Inc.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

IPC: G06F12/02 ,  G06F12/0864 ,  G06F12/0893

Abstract: Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.

公开(公告)号：US20200310694A1

公开(公告)日：2020-10-01

申请号：US16832737

申请日：2020-03-27

Applicant: Micron Technology, Inc.

Inventor： Shanyuan Gao ,  Sen Ma ,  Moon Mark Hur ,  Jaime Cummins

IPC: G06F3/06

Abstract: Methods, systems, and apparatuses related to computational storage are described. For example, storage accessible to an accelerator may be shared between and, accessible to either of, a host and the accelerator. A computational storage system may include storage providing a portion of a shared file system accessible by a host and by accelerator logic of the computational storage system. Host interface logic may be configured to receive a storage command from the host to store data on the storage at a time the data is created. The host interface logic may be further configured to receive a storage command from the host for the accelerator logic to perform a computational task using the stored data on the storage. The accelerator logic can perform the computational task using the stored data on the storage.