公开(公告)号：US20220229600A1

公开(公告)日：2022-07-21

申请号：US17570024

申请日：2022-01-06

Applicant: Micron Technology, Inc.

Inventor： Saira Samar Malik ,  Chinnakrishnan Ballapuram ,  Taeksang Song

IPC: G06F3/06

Abstract: Methods, systems, and devices for opportunistic data movement are described. A memory device may include a non-volatile memory and a volatile memory that operates as a cache for the non-volatile memory. The memory device may receive a write command from a host device. The write command may be associated with a row of a bank in a volatile memory. The memory device may write data associated with the write command to a buffer that is associated with the bank and that is coupled with the volatile memory. And the memory device may communicate the data from the buffer to the volatile memory based on the write command and before a pre-charge command for the row of the bank is received from the host device.

公开(公告)号：US20220066948A1

公开(公告)日：2022-03-03

申请号：US17395301

申请日：2021-08-05

Applicant: Micron Technology, Inc.

Inventor： Saira Samar Malik ,  Taeksang Song ,  Chinnakrishnan Ballapuram

IPC: G06F12/12 ,  G06F12/02

Abstract: Methods, systems, and devices for cache management in a memory subsystem are described. A device may determine to perform an eviction procedure for a bank of a volatile memory that operates as a cache for a non-volatile memory. The eviction procedure may save data from the bank of the volatile memory to the non-volatile memory. The device may determine an activity status for at least one buffer in a pool of buffers that are coupled with the volatile memory and the non-volatile memory. The device may select the at least one buffer in the pool of buffers for the eviction procedure for the bank of the volatile memory based at least in part on the activity status for that buffer.

公开(公告)号：US20220066698A1

公开(公告)日：2022-03-03

申请号：US17395300

申请日：2021-08-05

Applicant: Micron Technology, Inc.

Inventor： Chinnakrishnan Ballapuram ,  Saira Samar Malik ,  Taeksang Song

IPC: G06F3/06

Abstract: Methods, systems, and devices for efficient command scheduling for multiple memories are described. A device may be coupled with a non-volatile memory that may operate as main memory and a volatile memory that may operate as a cache for the non-volatile memory. The device may receive an access command from a host device. The device may determine the appropriate memory from multiple memories for servicing the access command and communicate the access command to the memory.

公开(公告)号：US20220035739A1

公开(公告)日：2022-02-03

申请号：US17390097

申请日：2021-07-30

Applicant: Micron Technology, Inc.

Inventor： Chinnakrishnan Ballapuram ,  Taeksang Song ,  Saira Samar Malik

IPC: G06F12/0802 ,  G06F3/06

Abstract: Methods, systems, and devices for metadata management for a cache are described. An interface controller may include a first array and a second array that store metadata for a cache memory. The interface controller may receive an activate command associated with a row of the cache memory. In response to the activate command, the interface controller may communicate storage information for the row of the volatile memory from a first array to a first register. The interface controller may receive an access command associated with the row of the cache memory. In response to the access command and based on the storage information in the first register, the interface controller may communicate validity information for the row from a second array to the first register or dirty information for the row from the second array to a second register.