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    Opportunistic data movement
    2.
    发明授权
    Opportunistic data movement 有权

    公开(公告)号：US11972145B2

    公开(公告)日：2024-04-30

    申请号：US17570024

    申请日：2022-01-06

    Applicant: Micron Technology, Inc.

    Inventor： Saira Samar Malik ,  Chinnakrishnan Ballapuram ,  Taeksang Song

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

    Abstract: Methods, systems, and devices for opportunistic data movement are described. A memory device may include a non-volatile memory and a volatile memory that operates as a cache for the non-volatile memory. The memory device may receive a write command from a host device. The write command may be associated with a row of a bank in a volatile memory. The memory device may write data associated with the write command to a buffer that is associated with the bank and that is coupled with the volatile memory. And the memory device may communicate the data from the buffer to the volatile memory based on the write command and before a pre-charge command for the row of the bank is received from the host device.

    Hazard detection in a multi-memory device
    3.
    发明授权
    Hazard detection in a multi-memory device 有权

    公开(公告)号：US11797231B2

    公开(公告)日：2023-10-24

    申请号：US17584104

    申请日：2022-01-25

    Applicant: Micron Technology, Inc.

    Inventor： Taeksang Song ,  Saira Samar Malik ,  Chinnakrishnan Ballapuram

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/068 ,  G06F3/0614

    Abstract: Methods, systems, and devices for hazard detection in a multi-memory device are described. A device may receive a first command that indicates a first bank address, a first row address, and a first column address. Based on the first bank address, the device may select a buffer for a hazard detection procedure that detects hazardous commands. The device may compare, as part of the hazard detection procedure, the first row address and the first column address from the first command with a second row address and a second column address from a second command in the buffer. The device may determine whether the first command and the second command are hazardous commands based on comparing the first row address and the first column address from the first command with the second row address and the second column address from the second command.

    MEMORY WEAR MANAGEMENT
    4.
    发明申请
    MEMORY WEAR MANAGEMENT 有权

    公开(公告)号：US20220011944A1

    公开(公告)日：2022-01-13

    申请号：US17349634

    申请日：2021-06-16

    Applicant: Micron Technology, Inc.

    Inventor： Saira Samar Malik ,  Hyunyoo Lee ,  Chinnakrishnan Ballapuram ,  Taeksang Song ,  Kang-Yong Kim

    IPC: G06F3/06 ,  G06F12/02

    Abstract: Methods, systems, and devices for memory wear management are described. A device may include an interface controller and a non-volatile memory. The interface controller may manage wear-leveling procedures for memory banks in the non-volatile memory. For example, the interface controller may select a row in a memory bank for the wear-leveling procedure. The interface controller may store data from the row in a buffer in the interface controller. The interface controller may then transfer the data to the non-volatile memory so that the non-volatile memory can write the data to a second row of the memory bank.

    Techniques for partial writes
    5.
    发明授权
    Techniques for partial writes 有权

    公开(公告)号：US12056395B2

    公开(公告)日：2024-08-06

    申请号：US17456994

    申请日：2021-11-30

    Applicant: Micron Technology, Inc.

    Inventor： Taeksang Song ,  Chinnakrishnan Ballapuram ,  Saira Samar Malik

    IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0868

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0673 ,  G06F12/0238 ,  G06F12/0868

    Abstract: Methods, systems, and devices for improved techniques for partial writes are described. A memory device may include a non-volatile memory and a volatile memory configured to operate as a cache for the non-volatile memory. The memory device may receive, from a host device, a write command for a first data set provided by the host device. Based on the write command, the memory device may store the first data set in a buffer coupled with a volatile memory. After storing the first data set in the buffer, the memory device may communicate to the volatile memory a set of data that includes the first data set and a second data set. The first data set and the second data may be associated with adjacent addresses for the volatile memory and may each have sizes smaller than a threshold size associated with the volatile memory.

    Memory bypass for error detection and correction
    7.
    发明授权
    Memory bypass for error detection and correction 有权

    公开(公告)号：US11720258B2

    公开(公告)日：2023-08-08

    申请号：US17349626

    申请日：2021-06-16

    Applicant: Micron Technology, Inc.

    Inventor： Chinnakrishnan Ballapuram ,  Saira S. Malik ,  Taeksang Song

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0673

    Abstract: Methods, systems, and devices for compressed logical-to-physical mapping for a memory bypass for error detection and correction are described. A memory device may include error detection and correction circuitry for detecting and correcting errors in data that is read from a memory array of the memory device. To reduce read latencies, the memory device may include bypass circuitry that enables it to transmit the data to the host device before or during error detection. If the memory device determines that the data is erroneous, the memory device may transmit an alert to the host device concurrently with or after transmitting the data. The memory device may perform error correction on the data and store corrected data in a register. Based on receiving an alert, the host device may issue one or more additional read commands to re-read the data from the memory bank or read the corrected data from the register.

    Direct testing of in-package memory
    8.
    发明授权
    Direct testing of in-package memory 有权

    公开(公告)号：US11587633B2

    公开(公告)日：2023-02-21

    申请号：US17349612

    申请日：2021-06-16

    Applicant: Micron Technology, Inc.

    Inventor： Taeksang Song ,  Hyunyoo Lee ,  Saira Samar Malik ,  Kang-Yong Kim

    IPC: G11C29/10 ,  G11C29/36 ,  G11C29/14 ,  G11C29/18 ,  G11C29/12

    Abstract: Methods, systems, and devices for direct testing of in-package memory are described. A memory subsystem package may include non-volatile memory, volatile memory that may be configured as a cache, and a controller. The memory subsystem may support direct access to the non-volatile memory for testing the non-volatile memory in the package using a host interface of the memory subsystem rather than using dedicated contacts on the package. To ensure deterministic behavior during testing operations, the memory subsystem may, when operating with a test mode enabled, forward commands received from a host device (such as automated test equipment) to a memory interface of the non-volatile memory and bypass the cache-related circuitry. The memory subsystem may include a separate conductive path that bypasses the cache for forwarding commands and addresses to the memory interface during testing.

    Metadata management for a cache
    9.
    发明授权
    Metadata management for a cache 有权

    公开(公告)号：US11526442B2

    公开(公告)日：2022-12-13

    申请号：US17390097

    申请日：2021-07-30

    Applicant: Micron Technology, Inc.

    Inventor： Chinnakrishnan Ballapuram ,  Taeksang Song ,  Saira Samar Malik

    IPC: G06F12/00 ,  G06F12/0802 ,  G06F3/06

    Abstract: Methods, systems, and devices for metadata management for a cache are described. An interface controller may include a first array and a second array that store metadata for a cache memory. The interface controller may receive an activate command associated with a row of the cache memory. In response to the activate command, the interface controller may communicate storage information for the row of the volatile memory from a first array to a first register. The interface controller may receive an access command associated with the row of the cache memory. In response to the access command and based on the storage information in the first register, the interface controller may communicate validity information for the row from a second array to the first register or dirty information for the row from the second array to a second register.

    POWER MODE CONTROL IN A MULTI-MEMORY DEVICE
    10.
    发明申请
    POWER MODE CONTROL IN A MULTI-MEMORY DEVICE 有权

    公开(公告)号：US20220350535A1

    公开(公告)日：2022-11-03

    申请号：US17585298

    申请日：2022-01-26

    Applicant: Micron Technology, Inc.

    Inventor： Taeksang Song ,  Saira Samar Malik ,  Chinnakrishnan Ballapuram

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for power mode control in a multi-memory device are described. An apparatus may include a non-volatile memory and a volatile memory. The apparatus may operate the volatile memory in a first power mode and the non-volatile memory in a second power mode. The apparatus may transition the volatile memory from the first power mode to a third power mode based on a power mode command from a host device. The apparatus may transition the non-volatile memory from the second power mode to a fourth power mode that consumes less power than the second power mode irrespective of the command from the host device and based on a quantity of queued commands for the non-volatile memory being less than a threshold quantity.

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