公开(公告)号：US11526306B1

公开(公告)日：2022-12-13

申请号：US17323628

申请日：2021-05-18

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert M. Walker

IPC: G06F3/06

Abstract: Methods, systems, and apparatus for command scheduling in a memory subsystem according to a selected scheduling ordering are described. Scheduling orderings are determined for a set of commands, where a scheduling ordering identifies an order by which a memory subsystem controller is to issue each command in the set of commands to the memory device. Scores are calculated for the scheduling orderings. A score of the plurality of scores includes a measure of performance of execution of the set of commands according to the scheduling ordering. A scheduling ordering is selected from the scheduling orderings based on the scores, and a command is issued to the memory device according to the scheduling ordering.

公开(公告)号：US11262946B2

公开(公告)日：2022-03-01

申请号：US16694105

申请日：2019-11-25

Applicant: Micron Technology, Inc.

Inventor： Dhawal Bavishi ,  Patrick A. La Fratta

IPC: G06F3/06 ,  G06F12/0802

Abstract: Various embodiments described herein provide for selectively sending a cache-based read command, such as a speculative read (SREAD) command in accordance with a Non-Volatile Dual In-Line Memory Module-P (NVDIMM-P) memory protocol, to a memory sub-system.

公开(公告)号：US11256437B2

公开(公告)日：2022-02-22

申请号：US16195071

申请日：2018-11-19

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Paul Rosenfeld ,  Patrick A. La Fratta

IPC: G06F3/06

Abstract: Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster.

公开(公告)号：US11163473B2

公开(公告)日：2021-11-02

申请号：US16195018

申请日：2018-11-19

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Paul Rosenfeld ,  Patrick A. La Fratta

IPC: G06F3/06

Abstract: Methods, systems, and devices for performing data migration operations using a memory system are described. The memory system may include a data migration component, such as a driver, for facilitating the transfer of data between a first memory device that may implement a first memory technology (e.g., having a relatively fast access speed) and a second memory device that may implement a second memory technology (e.g., having a relatively large capacity). The component may indicate the data migration operation to a second component (e.g., a controller) of the memory system. The second component may initiate the transfer of data between the first memory device and the second memory device based on the receiving the indication of the data migration operation. In some cases, the transfer of data between the first memory device and the second memory device may occur within the memory system without being transferred through a host device.

公开(公告)号：US11016885B2

公开(公告)日：2021-05-25

申请号：US16285909

申请日：2019-02-26

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker ,  Chandrasekhar Nagarajan

IPC: G06F13/00 ,  G06F13/28 ,  G06F12/06 ,  G06F12/04 ,  G06F9/30

Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.

公开(公告)号：US10990321B2

公开(公告)日：2021-04-27

申请号：US16280607

申请日：2019-02-20

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker

IPC: G06F3/06

Abstract: Commands in a command queue are received and scheduled. For each of the commands, scheduling includes determining an age of a command based on an entrance time of the command in the command queue. When the age of the command satisfies a first threshold, marking all other commands in the command queue as not issuable when the command is a deterministic command, and marking all other commands in the command queue as not issuable when the command is a non-deterministic command and the intermediate command queue is not empty. Scheduling the command further includes determining whether the command is a read command and marking the command as not issuable when the command is a non-deterministic read command and the intermediate command queue is empty.

公开(公告)号：US20210056052A1

公开(公告)日：2021-02-25

申请号：US17093104

申请日：2020-11-09

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert M. Walker

IPC: G06F13/16 ,  G06F3/06 ,  G06F12/06

Abstract: Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.

公开(公告)号：US20190317697A1

公开(公告)日：2019-10-17

申请号：US16117356

申请日：2018-08-30

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert M. Walker

IPC: G06F3/06

Abstract: Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.

公开(公告)号：US20190317693A1

公开(公告)日：2019-10-17

申请号：US15951896

申请日：2018-04-12

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert M. Walker

IPC: G06F3/06

Abstract: Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.

公开(公告)号：US10409739B2

公开(公告)日：2019-09-10

申请号：US15791886

申请日：2017-10-24

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert M. Walker

IPC: G06F12/00 ,  G06F13/16 ,  G06F3/06 ,  G06F12/06

Abstract: Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.