公开(公告)号：US20240411466A1

公开(公告)日：2024-12-12

申请号：US18808887

申请日：2024-08-19

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Sujeet Ayyapureddi ,  Edmund J. Gieske ,  Cagdas Dirik ,  Ameen D. Akel ,  Elliott C. Cooper-Balis ,  Amitava Majumdar ,  Robert M. Walker ,  Danilo Caraccio

IPC: G06F3/06

Abstract: Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.

公开(公告)号：US11886348B2

公开(公告)日：2024-01-30

申请号：US18117820

申请日：2023-03-06

Applicant: Micron Technology, Inc.

Inventor： Laurent Isenegger ,  Robert M. Walker ,  Cagdas Dirik

IPC: G06F3/06 ,  G06F12/0862 ,  G06F12/0831

CPC classification number: G06F12/0862 ,  G06F3/061 ,  G06F3/0658 ,  G06F3/0683 ,  G06F12/0835 ,  G06F2212/283

Abstract: A method includes receiving, at a direct memory access (DMA) controller of a memory device, a first command from a first cache controller coupled to the memory device to prefetch first data from the memory device and sending the prefetched first data, in response to receiving the first command, to a second cache controller coupled to the memory device. The method can further include receiving a second command from a second cache controller coupled to the memory device to prefetch second data from the memory device, and sending the prefetched second data, in response to receiving the second command, to a third cache controller coupled to the memory device.

公开(公告)号：US20240028260A1

公开(公告)日：2024-01-25

申请号：US18340589

申请日：2023-06-23

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker

IPC: G06F3/06 ,  G06F13/42 ,  G11C7/10

CPC classification number: G06F3/0659 ,  G06F13/4282 ,  G06F3/0688 ,  G06F3/061 ,  G11C7/1003

Abstract: The present disclosure includes apparatuses and methods related to memory module interfaces. A memory module, which may include volatile memory or nonvolatile memory, or both, may be configured to communicate with a host device via one interface and to communicate with another memory module using a different interface. Memory modules may thus be added or removed from a system without impacting a PCB-based bus to the host, and memory modules may communicate with one another without accessing a bus to the host. The host interface may be configured according to one protocol or standard, and other interfaces between memory modules may be configured according to other protocols or standards.

公开(公告)号：US11809332B2

公开(公告)日：2023-11-07

申请号：US17548948

申请日：2021-12-13

Applicant: Micron Technology, Inc.

Inventor： Paul Rosenfeld ,  Robert M. Walker

IPC: G06F12/1045 ,  G06F12/02 ,  G06F12/0862 ,  G06F12/1009

CPC classification number: G06F12/1063 ,  G06F12/0238 ,  G06F12/0862 ,  G06F12/1009 ,  G06F12/1054

Abstract: An apparatus includes circuitry couplable to a host system and a memory device. The circuitry is configured to determine whether a page table maintained on the circuitry includes a physical address of the memory device corresponding to a virtual address associated with a TLB fill request from the host system. Responsive to determining that the page table includes the physical address, the circuitry provides signaling indicative of a completion to the TLB fill request to the host system, prefetch a page of data at the physical address from the memory device using the physical address from the page table, and provide signaling indicative of the page of data to the host system.

公开(公告)号：US11734071B2

公开(公告)日：2023-08-22

申请号：US17464546

申请日：2021-09-01

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Paul Rosenfeld

IPC: G06F9/50 ,  G06F12/12

CPC classification number: G06F9/5016 ,  G06F12/12 ,  G06F2212/1021

Abstract: A method includes allocating, via a tier allocation component, a first portion of data to a first tier memory component and writing the first portion of data to the first tier memory component in response to a first tier free list having an available entry. The method further includes evicting a second portion of data from the first tier memory component in response to the first tier free list being empty when the first portion of data is allocated to the first tier memory component and writing the first portion of data to the first tier memory component in response to evicting the second portion of data.

公开(公告)号：US20230098454A1

公开(公告)日：2023-03-30

申请号：US17485060

申请日：2021-09-24

Applicant: Micron Technology, Inc.

Inventor： Dhawal Bavishi ,  Robert M. Walker ,  Laurent Isenegger

IPC: G06F3/06

Abstract: A system includes a first controller configured to adjust a count of a number of first transactions and adjust a count of a number of second transactions. The count of the number of first transactions and the count of the number of second transactions are adjusted when a first transaction or second transaction is either received or executed by a second controller. The second controller is coupled to the first controller and is configured to limit the number of first transactions to a particular quantity of outstanding first transactions, limit the number of second transactions to a particular quantity of outstanding second transactions, and limit a number of total transactions to a particular quantity of outstanding total transactions.

公开(公告)号：US20220398013A1

公开(公告)日：2022-12-15

申请号：US17893118

申请日：2022-08-22

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  James A. Hall, JR. ,  Frank F. Ross

IPC: G06F3/06 ,  G06F12/00 ,  G06F12/02 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations. The memory device can be a non-volatile dual in-line memory module (NVDIMM) device.

公开(公告)号：US11526306B1

公开(公告)日：2022-12-13

申请号：US17323628

申请日：2021-05-18

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert M. Walker

IPC: G06F3/06

Abstract: Methods, systems, and apparatus for command scheduling in a memory subsystem according to a selected scheduling ordering are described. Scheduling orderings are determined for a set of commands, where a scheduling ordering identifies an order by which a memory subsystem controller is to issue each command in the set of commands to the memory device. Scores are calculated for the scheduling orderings. A score of the plurality of scores includes a measure of performance of execution of the set of commands according to the scheduling ordering. A scheduling ordering is selected from the scheduling orderings based on the scores, and a command is issued to the memory device according to the scheduling ordering.

公开(公告)号：US20220156209A1

公开(公告)日：2022-05-19

申请号：US17588777

申请日：2022-01-31

Applicant: Micron Technology, Inc.

Inventor： Frank F. Ross ,  Robert M. Walker

IPC: G06F13/28 ,  H04L1/00 ,  G06F13/16 ,  G06F11/10

Abstract: The present disclosure includes apparatuses and methods related to transaction identification. An example apparatus can determine a transaction identification (TID) associated with a command by comparing a host transaction identification (TID) record with a memory device transaction identification (TID) record.

公开(公告)号：US20220137882A1

公开(公告)日：2022-05-05

申请号：US17575878

申请日：2022-01-14

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Frank F. Ross

IPC: G06F3/06 ,  G06F13/42 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can execute a read command that includes a first chunk of data and a second chunk of data by assigning a first read identification (RID) number to the first chunk of data and a second RID number to the second chunk of data, sending the first chunk of data and the first RID number to a host, and sending the second chunk of data and the second RID number to the host. The apparatus can be a non-volatile dual in-line memory module (NVDIMM) device.