公开(公告)号：US20090040668A1

公开(公告)日：2009-02-12

申请号：US11837306

申请日：2007-08-10

Applicant: Zi-Ping Chen ,  Ming-Dao Ker ,  Hsin-Chin Jiang

Inventor： Zi-Ping Chen ,  Ming-Dao Ker ,  Hsin-Chin Jiang

IPC: H02H9/04

CPC classification number: H01L27/0285

Abstract: An ESD protection circuit that protects a mixed-voltage input/output (I/O) buffer circuit in an integrated circuit is provided. The ESD protection circuit includes an ESD discharging circuit coupled to the I/O pad and ESD detection circuit coupled to the discharging circuit providing a means for detecting an ESD and triggering the discharging circuit to conduct the ESD to ground. The ESD discharging circuit comprises stacked NMOS transistors or a field oxide device (FOD). The protection circuit can also be used in an ESD protection circuit for a high-voltage-tolerant input pad or to protect multiple input pads and/or multiple I/O pads in an integrated circuit.

Abstract translation: 提供了一种保护集成电路中混合电压输入/输出（I / O）缓冲电路的ESD保护电路。 ESD保护电路包括耦合到I / O焊盘的ESD放电电路和耦合到放电电路的ESD检测电路，其提供用于检测ESD并触发放电电路以将ESD导电到地的装置。 ESD放电电路包括堆叠的NMOS晶体管或场氧化物器件（FOD）。 保护电路也可以用于高耐压输入焊盘的ESD保护电路中，或者用于保护集成电路中的多个输入焊盘和/或多个I / O焊盘。

公开(公告)号：US07304827B2

公开(公告)日：2007-12-04

申请号：US10428047

申请日：2003-05-02

Applicant: Zi-Ping Chen ,  Ming-Dao Ker ,  Hsin-Chin Jiang

Inventor： Zi-Ping Chen ,  Ming-Dao Ker ,  Hsin-Chin Jiang

IPC: H02H9/00

CPC classification number: H01L27/0285 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An ESD protection circuit that protects a mixed-voltage input/output (I/O) buffer circuit in an integrated circuit is provided. The ESD protection circuit includes an ESD discharging circuit coupled to the I/O pad and ESD detection circuit coupled to the discharging circuit providing a means for detecting an ESD and triggering the discharging circuit to conduct the ESD to ground. The ESD discharging circuit comprises stacked NMOS transistors or a field oxide device (FOD). The protection circuit can also be used in an ESD protection circuit for a high-voltage-tolerant input pad or to protect multiple input pads and/or multiple I/O pads in an integrated circuit.

Abstract translation: 提供了一种保护集成电路中混合电压输入/输出（I / O）缓冲电路的ESD保护电路。 ESD保护电路包括耦合到I / O焊盘的ESD放电电路和耦合到放电电路的ESD检测电路，其提供用于检测ESD并触发放电电路以将ESD导电到地的装置。 ESD放电电路包括堆叠的NMOS晶体管或场氧化物器件（FOD）。 保护电路也可以用于高耐压输入焊盘的ESD保护电路中，或者用于保护集成电路中的多个输入焊盘和/或多个I / O焊盘。