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1.发明授权公开(公告)号：US08829775B2
公开(公告)日：2014-09-09
申请号：US13464506
申请日：2012-05-04
CPC分类号： H01J9/02 , H01J17/066
摘要： The present invention discloses a semiconductor-based planar micro-tube discharger structure and a method for fabricating the same. The method comprises steps: forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap; forming an insulating layer over the patterned electrodes and the separating block and filling the insulating layer into the gap. Thereby are formed at least two discharge paths. The method can fabricate a plurality discharge paths in a semiconductor structure. Therefore, the structure of the present invention has very high reliability and reusability.
摘要翻译： 本发明公开了一种基于半导体的平面微管放电器结构及其制造方法。 该方法包括以下步骤：在衬底上形成由间隙分开的两个图案化电极和布置在间隙中的至少一个分隔块; 在图案化电极和分离块上形成绝缘层，并将绝缘层填充到间隙中。 由此形成至少两个排出路径。 该方法可以在半导体结构中制造多个放电路径。 因此，本发明的结构具有非常高的可靠性和可重用性。
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公开(公告)号：US08552530B2
公开(公告)日：2013-10-08
申请号：US12848531
申请日：2010-08-02
IPC分类号： H01L29/06
CPC分类号： H01L27/0259
摘要： A vertical transient voltage suppressor for protecting an electronic device is disclosed. The vertical transient voltage includes a conductivity type substrate having highly doping concentration; a first type lightly doped region is arranged on the conductivity type substrate, wherein the conductivity type substrate and the first type lightly doped region respectively belong to opposite types; a first type heavily doped region and a second type heavily doped region are arranged in the first type lightly doped region, wherein the first and second type heavily doped regions and the conductivity type substrate belong to same types; and a deep first type heavily doped region is arranged on the conductivity type substrate and neighbors the first type lightly doped region, wherein the deep first type heavily doped region and the first type lightly doped region respectively belong to opposite types, and wherein the deep first type heavily doped region is coupled to the first type heavily doped region.
摘要翻译： 公开了一种用于保护电子设备的垂直瞬态电压抑制器。 垂直瞬变电压包括具有高掺杂浓度的导电型衬底; 导电型衬底上布置有第一类型轻掺杂区域，其中导电类型衬底和第一类型轻掺杂区域分别属于相反类型; 第一类型重掺杂区和第二类重掺杂区布置在第一类型轻掺杂区域中，其中第一和第二类型重掺杂区和导电类型衬底属于相同类型; 并且深度第一类型重掺杂区域布置在导电类型衬底上并且与第一类型轻掺杂区域相邻，其中深第一类型重掺杂区域和第一类型轻掺杂区域分别属于相反类型，并且其中深第一类型重掺杂区域 型重掺杂区域耦合到第一类型重掺杂区域。
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3.发明申请公开(公告)号：US20130221834A1
公开(公告)日：2013-08-29
申请号：US13464506
申请日：2012-05-04
CPC分类号： H01J9/02 , H01J17/066
摘要： The present invention discloses a semiconductor-based planar micro-tube discharger structure and a method for fabricating the same. The method comprises steps: forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap; forming an insulating layer over the patterned electrodes and the separating block and filling the insulating layer into the gap. Thereby are formed at least two discharge paths. The method can fabricate a plurality discharge paths in a semiconductor structure. Therefore, the structure of the present invention has very high reliability and reusability.
摘要翻译： 本发明公开了一种基于半导体的平面微管放电器结构及其制造方法。 该方法包括以下步骤：在衬底上形成由间隙分开的两个图案化电极和布置在间隙中的至少一个分隔块; 在图案化电极和分离块上形成绝缘层，并将绝缘层填充到间隙中。 由此形成至少两个排出路径。 该方法可以在半导体结构中制造多个放电路径。 因此，本发明的结构具有非常高的可靠性和可重用性。
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公开(公告)号：US08304838B1
公开(公告)日：2012-11-06
申请号：US13216016
申请日：2011-08-23
IPC分类号： H01L21/00
CPC分类号： H01L27/0255
摘要： An electrostatic discharge protection device structure is disclosed, which comprises a semiconductor substrate and an N-type epitaxial layer arranged on the semiconductor substrate. At least one snapback cascade structure is arranged in the N-type epitaxial layer, wherein the snapback cascade structure further comprises first and second P-type wells arranged in the N-type epitaxial layer. First and second heavily doped areas arranged in the first P-type well respectively belong to opposite types. And, third and fourth heavily doped areas arranged in the second P-type well respectively belong to opposite types, wherein the second and third heavily doped areas respectively belong to opposite types and are electrically connected with each other. When the first heavily doped area receives an ESD signal, an ESD current flows from the first heavily doped area to the fourth heavily doped area through the first P-type well, the N-type epitaxial layer, and the second P-type well.
摘要翻译： 公开了一种静电放电保护器件结构，其包括半导体衬底和布置在半导体衬底上的N型外延层。 在N型外延层中布置有至少一个快速反应级联结构，其中快速回退级联结构还包括布置在N型外延层中的第一和第二P型阱。 排列在第一P型井中的第一和第二重掺杂区域分别属于相反的类型。 并且，排列在第二P型阱中的第三和第四重掺杂区域分别属于相反的类型，其中第二和第三重掺杂区域分别属于相反的类型并且彼此电连接。 当第一重掺杂区域接收到ESD信号时，ESD电流通过第一P型阱，N型外延层和第二P型阱从第一重掺杂区流动到第四重掺杂区。
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公开(公告)号：US08116049B2
公开(公告)日：2012-02-14
申请号：US12625449
申请日：2009-11-24
申请人： Ming-Dou Ker , Hsin-Chin Jiang , Wen-Yi Chen
发明人： Ming-Dou Ker , Hsin-Chin Jiang , Wen-Yi Chen
IPC分类号： H02H3/22
CPC分类号： H02H9/046 , H02H1/0007
摘要： The invention discloses a transient voltage detection circuit suitable for an electronic system. The electronic system includes a high voltage line and a low voltage line. The transient voltage detection circuit includes at least one detection circuit and a judge module. Each detection circuit includes a P-typed transistor and/or an N-typed transistor, a capacitor and a detection node. The transistor is coupled with the capacitor, and the detection node is located between the transistor and the capacitor. The judge module is coupled to each of the detection nodes. The judge module generates a judgment according to voltage levels of the detection nodes. Accordingly, the transient voltage detection circuit is formed. The electronic system may selectively execute a protective action according to the judgment.
摘要翻译： 本发明公开了一种适用于电子系统的瞬态电压检测电路。 电子系统包括高压线路和低压线路。 瞬态电压检测电路包括至少一个检测电路和判断模块。 每个检测电路包括P型晶体管和/或N型晶体管，电容器和检测节点。 晶体管与电容器耦合，检测节点位于晶体管和电容器之间。 判断模块耦合到每个检测节点。 判断模块根据检测节点的电压电平生成判断。 因此，形成了瞬态电压检测电路。 电子系统可以根据判断选择性地执行保护动作。
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公开(公告)号：US20120025350A1
公开(公告)日：2012-02-02
申请号：US12848531
申请日：2010-08-02
IPC分类号： H01L29/06
CPC分类号： H01L27/0259
摘要： A vertical transient voltage suppressor for protecting an electronic device is disclosed. The vertical transient voltage includes a conductivity type substrate having highly doping concentration; a first type lightly doped region is arranged on the conductivity type substrate, wherein the conductivity type substrate and the first type lightly doped region respectively belong to opposite types; a first type heavily doped region and a second type heavily doped region are arranged in the first type lightly doped region, wherein the first and second type heavily doped regions and the conductivity type substrate belong to same types; and a deep first type heavily doped region is arranged on the conductivity type substrate and neighbors the first type lightly doped region, wherein the deep first type heavily doped region and the first type lightly doped region respectively belong to opposite types, and wherein the deep first type heavily doped region is coupled to the first type heavily doped region.
摘要翻译： 公开了一种用于保护电子设备的垂直瞬态电压抑制器。 垂直瞬变电压包括具有高掺杂浓度的导电型衬底; 导电型衬底上布置有第一类型轻掺杂区域，其中导电类型衬底和第一类型轻掺杂区域分别属于相反类型; 第一类型重掺杂区和第二类重掺杂区布置在第一类型轻掺杂区域中，其中第一和第二类型重掺杂区和导电类型衬底属于相同类型; 并且深度第一类型重掺杂区域布置在导电类型衬底上并且与第一类型轻掺杂区域相邻，其中深第一类型重掺杂区域和第一类型轻掺杂区域分别属于相反类型，并且其中深第一类型重掺杂区域 型重掺杂区域耦合到第一类型重掺杂区域。
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公开(公告)号：US07915638B2
公开(公告)日：2011-03-29
申请号：US12113912
申请日：2008-05-01
IPC分类号： H01L29/66
CPC分类号： H01L27/0262 , H01L29/747 , H01L29/87
摘要： The present invention discloses a symmetric bidirectional silicon-controlled rectifier, which comprises: a substrate; a buried layer formed on the substrate; a first well, a middle region and a second well, which are sequentially formed on the buried layer side-by-side; a first semiconductor area and a second semiconductor area both formed inside the first well; a third semiconductor area formed in a junction between the first well and the middle region, wherein a first gate is formed over a region between the second and third semiconductor areas; a fourth semiconductor area and a fifth semiconductor area both formed inside the second well; a sixth semiconductor area formed in a junction between the second well and the middle region, wherein a second gate is formed over a region between the fifth and sixth semiconductor areas.
摘要翻译： 本发明公开了一种对称双向硅控整流器，其包括：衬底; 形成在基板上的掩埋层; 第一阱，中间区域和第二阱，并排地依次形成在掩埋层上; 第一半导体区域和第二半导体区域都形成在第一阱内; 形成在所述第一阱和所述中间区域之间的接合处的第三半导体区域，其中在所述第二和第三半导体区域之间的区域上形成第一栅极; 形成在第二阱内的第四半导体区域和第五半导体区域; 形成在所述第二阱和所述中间区域之间的接合处的第六半导体区域，其中在所述第五和第六半导体区域之间的区域上形成第二栅极。
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公开(公告)号：US07817386B2
公开(公告)日：2010-10-19
申请号：US11907206
申请日：2007-10-10
IPC分类号： H02H9/00
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection circuit suitable for applying in an integrated circuit with separated power domains is provided. The circuit includes a P-type MOSFET coupled between a first circuit in a first power domain and a second circuit in a second power domain. A source terminal of the P-type MOSFET is coupled to a connection node for connecting the first circuit and the second circuit. A gate terminal of the P-type MOSFET is coupled to a positive power line of the second power domain. A drain terminal of the P-type MOSFET is coupled to a negative power line of the second power domain. A body terminal of the P-type MOSFET is also coupled to the connection node.
摘要翻译： 提供一种适用于具有分离电源域的集成电路中的ESD保护电路。 电路包括耦合在第一电源域中的第一电路和第二电源域中的第二电路之间的P型MOSFET。 P型MOSFET的源极端子连接到用于连接第一电路和第二电路的连接节点。 P型MOSFET的栅极端子耦合到第二电源域的正电源线。 P型MOSFET的漏极端子耦合到第二电源域的负电源线。 P型MOSFET的体式端子也耦合到连接节点。
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公开(公告)号：US07755871B2
公开(公告)日：2010-07-13
申请号：US11987222
申请日：2007-11-28
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An ESD protection circuit including a clamping module and a detecting module is provided. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a MOS capacitor. An output terminal of the triggering unit is used for triggering the clamping module. The resistor is coupled between the positive power line and an input terminal of the triggering unit. The MOS capacitor has a first end and a second end. The first end is coupled to the input terminal of the triggering unit. During a normal power operation, a switching terminal of the triggering unit enables the second end of the MOS capacitor to be coupled with the positive power line. Thereby, the gate tunneling leakage is eliminated and the problem of mistriggering is prevented.
摘要翻译： 提供了包括夹紧模块和检测模块的ESD保护电路。 夹紧模块耦合在正电源线和负电源线之间。 检测模块包括触发单元，电阻器和MOS电容器。 触发单元的输出端子用于触发夹紧模块。 电阻器耦合在正电源线和触发单元的输入端之间。 MOS电容器具有第一端和第二端。 第一端耦合到触发单元的输入端。 在正常电力操作期间，触发单元的开关端子使MOS电容器的第二端与正电源线耦合。 由此，消除了栅极隧道泄漏，并且防止了错误捕捉的问题。
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10.发明申请公开(公告)号：US20100155774A1
公开(公告)日：2010-06-24
申请号：US12342118
申请日：2008-12-23
申请人： Tang Kuei TSENG , Kun Hsien LIN , Hsin Chin JIANG
发明人： Tang Kuei TSENG , Kun Hsien LIN , Hsin Chin JIANG
IPC分类号： H01L29/747 , H01L21/332
CPC分类号： H01L29/87
摘要： A bidirectional transient voltage suppression device is disclosed. The bi-directional transient voltage suppression device comprises a semiconductor die. The semiconductor die has a multi-layer structure comprising a semiconductor substrate of a first conductivity type, a buried layer of a second conductivity type, an epitaxial layer, and five diffused regions. The buried layer and the semiconductor substrate form a first semiconductor junction. The first diffused region of the second conductivity type and the semiconductor substrate form a second semiconductor junction. The fourth diffused region of the first conductivity type and the third diffused region of the second conductivity type form a third semiconductor junction. The fifth diffused region of the first conductivity type and the second diffused region of the second conductivity type form a fourth semiconductor junction.
摘要翻译： 公开了一种双向瞬态电压抑制装置。 双向瞬态电压抑制装置包括半导体管芯。 半导体管芯具有包括第一导电类型的半导体衬底，第二导电类型的掩埋层，外延层和五个扩散区域的多层结构。 掩埋层和半导体衬底形成第一半导体结。 第二导电类型的第一扩散区域和半导体衬底形成第二半导体结。 第一导电类型的第四扩散区域和第二导电类型的第三扩散区域形成第三半导体结。 第一导电类型的第五扩散区域和第二导电类型的第二扩散区域形成第四半导体结。
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