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1.发明公开公开(公告)号：US20240363621A1
公开(公告)日：2024-10-31
申请号：US18770552
申请日：2024-07-11
发明人： Yu-Hung YEH , Wun-Jie LIN , Jam-Wem LEE
IPC分类号： H01L27/02 , H01L23/522 , H01L23/535 , H02H9/04
CPC分类号： H01L27/0288 , H01L23/5223 , H01L23/5228 , H01L23/535 , H01L27/0285 , H01L27/0292 , H02H9/046
摘要： An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.
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公开(公告)号：US20240234411A1
公开(公告)日：2024-07-11
申请号：US18617658
申请日：2024-03-27
发明人： MING-FANG LAI , LIANG-YU SU , HANG FAN
IPC分类号： H01L27/02 , H01L27/06 , H02H9/04 , H03K17/081 , H01L29/20 , H01L29/778
CPC分类号： H01L27/0266 , H01L27/0285 , H01L27/0288 , H01L27/0605 , H01L27/0629 , H02H9/046 , H03K17/08104 , H01L29/2003 , H01L29/778 , H02H9/04 , H02H9/044
摘要： The present disclosure provides an electrostatic discharge (ESD) protection circuit, coupled between a first reference terminal and a second reference terminal; the ESD protection circuit includes a first voltage divider, a second voltage divider, a first trigger circuit, a second trigger circuit, a first discharge component and a second discharge component. The first trigger circuit includes a first GaN based transistor, including a first source/drain and a second source/drain coupled to the first reference terminal and a gate coupled to the second reference terminal via the first voltage divider. The second trigger circuit includes a terminal coupled to the first reference terminal via the second voltage divider. The first discharge component includes a gate coupled between the first trigger circuit and the first voltage divider. The second discharge component includes a gate coupled between the second trigger circuit and the second voltage divider.
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公开(公告)号：US20230343779A1
公开(公告)日：2023-10-26
申请号：US17989481
申请日：2022-11-17
发明人： David Michael Rogers , Eric N. Mann , Eric Lee Swindlehurst , Toru Miyamae , Timothy John Williams , Ryuta Nagai , Sungkwon Lee , Ravindra M. Kapre , Mimi Xuefeng Zhao Qian , Yan Yi , Dung Si Ho , Boo Chin-Hua
IPC分类号： H01L27/02
CPC分类号： H01L27/0285 , H01L27/0288
摘要： An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.
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4.发明授权公开(公告)号：US11735582B2
公开(公告)日：2023-08-22
申请号：US16939248
申请日：2020-07-27
发明人： Min Cheol Kong
CPC分类号： H01L27/0285 , H02H9/046
摘要： An electrostatic discharge (ESD) protection circuit includes a plurality of transistors each including a gate terminal, a drain terminal, and a source terminal, a first connection line connected to the drain terminals of the plurality of transistors, a second connection line connected to the source terminals of the plurality of transistors, a third connection line connected to the gate terminals of the plurality of transistors, an external resistor connected to the third connection line, and a ground terminal connected to the external resistor. The external resistor includes a first resistor and a second resistor connected to each other in parallel.
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5.发明申请公开(公告)号：US20180287376A1
公开(公告)日：2018-10-04
申请号：US15476276
申请日：2017-03-31
申请人： NXP B.V.
发明人： Gijs de Raad
CPC分类号： H02H9/04 , H01L27/0248 , H01L27/027 , H01L27/0285 , H01L27/0629 , H01L28/20 , H01L28/40 , H02H9/046 , H03K19/00315
摘要： Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device includes an NMOS transistor configured to shunt current in response to an ESD pulse and a bigFET connected in parallel with the NMOS transistor. The NMOS transistor includes a source terminal, a gate terminal, and a body. The gate terminal and the body of the NMOS transistor are connected to the source terminal via a resistor. Other embodiments are also described.
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6.发明授权公开(公告)号：US10074643B2
公开(公告)日：2018-09-11
申请号：US15273220
申请日：2016-09-22
CPC分类号： H01L27/0248 , H01L23/60 , H01L27/0285 , H02H9/046 , H03K19/20
摘要： An integrated circuit with protection against transient electrical stress events includes a trigger circuit having a first detection circuit coupled to a first supply voltage, a second detection circuit coupled to a second supply voltage, and a rail clamp device. During a first type of electrical stress event, the rail clamp device is activated in response to a first output signal provided by the first detection circuit. During a second type of electrical stress event, the rail clamp device is activated in response to a second output signal provided by the second detection circuit.
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公开(公告)号：US20180233205A1
公开(公告)日：2018-08-16
申请号：US15700892
申请日：2017-09-11
发明人： Maya INAGAKI , Masaru KOYANAGI
IPC分类号： G11C16/22 , G11C16/30 , H02H9/04 , H01L25/065 , H01L27/02
CPC分类号： G11C16/22 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/30 , H01L23/60 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/18 , H01L27/0266 , H01L27/0285 , H01L27/0288 , H01L2224/04042 , H01L2224/05548 , H01L2224/0557 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/1703 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2225/06586 , H01L2924/15311 , H02H9/046 , H01L2924/00012 , H01L2924/00014 , H01L2924/00
摘要： According to an embodiment, a semiconductor storage device includes a first chip including a power supply protection circuit. The power supply protection circuit including: a resistor including a first end connected to the second pad; a first capacitor including a first end connected to a second end of the resistor; a first transistor including a first end connected to the second pad, a second end connected to a node with a signal of a value based on a voltage of the first end of the first capacitor, and a gate connected to the first pad; a first inverter including an input terminal connected to the second end of the first transistor; and a second transistor including a gate connected to an output terminal of the first inverter.
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公开(公告)号：US20180097359A1
公开(公告)日：2018-04-05
申请号：US15815473
申请日：2017-11-16
IPC分类号： H02H9/04 , H01L27/02 , H01L23/522 , H01L29/94
CPC分类号： H02H9/046 , H01L23/5228 , H01L27/0285 , H01L29/945 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection circuit includes a power clamp device, a timing circuit including a first resistor, a first capacitor that is connected with the first resistor at a first node, and a second capacitor that is connected to a second node, a logic gate including a first input connected with the first node, a second input connected with the second node, and an output connected with the power clamp device, and a decoder device connected with a first address pin and a second address pin. The first address pin and the second address pin are used to detect the power clamp device switching on at time of power on and draining current.
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9.发明申请公开(公告)号：US20180082992A1
公开(公告)日：2018-03-22
申请号：US15273220
申请日：2016-09-22
CPC分类号： H01L27/0248 , H01L23/60 , H01L27/0285 , H02H9/046
摘要： An integrated circuit with protection against transient electrical stress events includes a trigger circuit having a first detection circuit coupled to a first supply voltage, a second detection circuit coupled to a second supply voltage, and a rail clamp device. During a first type of electrical stress event, the rail clamp device is activated in response to a first output signal provided by the first detection circuit. During a second type of electrical stress event, the rail clamp device is activated in response to a second output signal provided by the second detection circuit.
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公开(公告)号：US09882376B2
公开(公告)日：2018-01-30
申请号：US14577145
申请日：2014-12-19
IPC分类号： H02H9/00 , H02H9/04 , H01L23/522 , H01L27/02 , H01L29/94
CPC分类号： H02H9/046 , H01L23/5228 , H01L27/0285 , H01L29/945 , H01L2924/0002 , H01L2924/00
摘要： Electrostatic discharge protection circuits and methods of fabricating an electrostatic discharge protection circuit, as well as methods of protecting an integrated circuit from a transient electrostatic discharge event. The electrostatic discharge protection circuit includes a power clamp device, a first timing circuit with a first resistor and a first capacitor that is coupled with the first resistor at a first node, and a second timing circuit including a second resistor and a second capacitor that is coupled with the second resistor at a second node. The electrostatic discharge protection circuit further includes a logic gate with a first input coupled with the first node, a second input coupled with the second node, and an output coupled with the power clamp device. The logic gate responds to voltages at the first and second nodes to control the impedance state of the power clamp device.
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