公开(公告)号：US06593920B2

公开(公告)日：2003-07-15

申请号：US09780492

申请日：2001-02-12

申请人： Haruhisa Okumura ,  Yukihide Ode

发明人： Haruhisa Okumura ,  Yukihide Ode

IPC分类号： G09G500

CPC分类号： H03K19/00384 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0289 ,  H03K19/018571

摘要： A level converter circuit includes an input terminal adapted to be supplied with a signal swinging from a first voltage to a second voltage lower than the first voltage; a first transistor having a gate electrode connected to the input terminal, and a source electrode connected to ground potential; a second transistor having a gate electrode connected to a drain electrode of the first transistor, a source electrode connected to a supply voltage, and a drain electrode connected to an output terminal; a load circuit connected between the gate electrode of the second transistor and the supply voltage; a third transistor having a source electrode connected to the input terminal, a drain electrode connected to the output terminal, and a gate electrode supplied with a DC voltage higher than the second voltage and lower than the first voltage. The level converter circuit outputs a third voltage higher than the second voltage when the input terminal is supplied with the first voltage, and the level converter circuit outputs the second voltage when the input terminal is supplied with the second voltage.

摘要翻译： 电平转换器电路包括适于被提供有从第一电压摆动到低于第一电压的第二电压的信号的输入端; 第一晶体管，其具有连接到所述输入端子的栅极电极和连接到地电位的源电极; 第二晶体管，具有连接到第一晶体管的漏极的栅电极，连接到电源电压的源电极和连接到输出端的漏电极; 连接在第二晶体管的栅电极和电源电压之间的负载电路; 第三晶体管，具有连接到输入端的源电极，连接到输出端的漏极和提供有高于第二电压并低于第一电压的直流电压的栅电极。 当输入端被提供第一电压时，电平转换器电路输出比第二电压高的第三电压，并且当输入端被提供第二电压时，电平转换器电路输出第二电压。

公开(公告)号：US08766900B2

公开(公告)日：2014-07-01

申请号：US13804946

申请日：2013-03-14

申请人： Yasuhiro Tanaka ,  Hironobu Isami ,  Haruhisa Iida ,  Hidenori Kikuchi ,  Yukihide Ode

发明人： Yasuhiro Tanaka ,  Hironobu Isami ,  Haruhisa Iida ,  Hidenori Kikuchi ,  Yukihide Ode

IPC分类号： G09G3/36 ,  G09G5/00

CPC分类号： G09G5/001 ,  G09G3/20 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/061 ,  G09G2310/08

摘要： There is a need for decreasing a variation in times for writing to TFT elements for pixels in a direction along the extension of a gate line in a liquid crystal display apparatus. A display apparatus includes a display panel having multiple gate lines and drain lines arranged in a matrix and a data driver for outputting a display data signal to each drain line. The data driver includes: an internal control signal generation circuit generating an internal control signal for setting a timing to output a data signal to a drain line of each block on a block basis by dividing the plurality of drain lines into multiple blocks; and a register circuit for recording a setting for division of the block, a setting for delay direction and width of a timing to output the data signal, and a setting for rising and falling of an internal control signal.

公开(公告)号：US20120050146A1

公开(公告)日：2012-03-01

申请号：US13200389

申请日：2011-09-23

申请人： Yasuhiro Tanaka ,  Hironobu Isami ,  Haruhisa Iida ,  Hidenori Kikuchi ,  Yukihide Ode

发明人： Yasuhiro Tanaka ,  Hironobu Isami ,  Haruhisa Iida ,  Hidenori Kikuchi ,  Yukihide Ode

IPC分类号： G09G3/36

CPC分类号： G09G5/001 ,  G09G3/20 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/061 ,  G09G2310/08

摘要： There is a need for decreasing a variation in times for writing to TFT elements for pixels in a direction along the extension of a gate line in a liquid crystal display apparatus. A display apparatus includes a display panel having multiple gate lines and drain lines arranged in a matrix and a data driver for outputting a display data signal to each drain line. The data driver includes an internal control signal generation circuit generating an internal control signal for setting a timing to output a data signal to a drain line of each block on a block basis by dividing the plurality of drain lines into multiple blocks; and a register circuit for recording a setting for division of the block, a setting for delay direction and width of a timing to output the data signal, and a setting for rising and falling of an internal control signal.

摘要翻译： 需要减少在液晶显示装置中沿着栅极线的延伸方向的像素的TFT元件的写入时间的变化。 显示装置包括具有排列成矩阵的多个栅极线和漏极线的显示面板和用于向每条漏极线输出显示数据信号的数据驱动器。 数据驱动器包括：内部控制信号产生电路，用于通过将多个排出线分成多个块，产生一个内部控制信号，该内部控制信号用于设置通过将块输出到每个块的排出线的数据信号的定时; 以及用于记录块的分割设置的寄存器电路，用于输出数据信号的定时的延迟方向和宽度的设置以及内部控制信号的上升和下降的设置。

公开(公告)号：US07821487B2

公开(公告)日：2010-10-26

申请号：US11639149

申请日：2006-12-15

申请人： Yasuhiro Tanaka ,  Hironobu Isami ,  Haruhisa Iida ,  Hidenori Kikuchi ,  Yukihide Ode

发明人： Yasuhiro Tanaka ,  Hironobu Isami ,  Haruhisa Iida ,  Hidenori Kikuchi ,  Yukihide Ode

IPC分类号： G09G3/36

CPC分类号： G09G5/001 ,  G09G3/20 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/061 ,  G09G2310/08

摘要： There is a need for decreasing a variation in times for writing to TFT elements for pixels in a direction along the extension of a gate line in a liquid crystal display apparatus. A display apparatus includes a display panel having multiple gate lines and multiple drain lines arranged in a matrix and a data driver for outputting a display data signal to each drain line. The data driver includes: an internal control signal generation circuit for generating an internal control signal for setting a timing to output a data signal to a drain line of each block on a block basis by dividing the plurality of drain lines into multiple blocks; and a register circuit for recording a setting for division of the block, a setting for a delay direction and a delay width of a timing to output the data signal, and a setting for rising and falling of an internal control signal.

摘要翻译： 需要减少在液晶显示装置中沿着栅极线的延伸方向的像素的TFT元件的写入时间的变化。 显示装置包括具有多个栅极线和排列成矩阵的多个漏极线的显示面板和用于向每条漏极线输出显示数据信号的数据驱动器。 数据驱动器包括：内部控制信号发生电路，用于通过将多个排出线分成多个块来产生用于设置定时的内部控制信号，以将数据信号以块的形式输出到每个块的漏极线; 以及用于记录块的分割设置的寄存器电路，延迟方向的设置和输出数据信号的定时的延迟宽度以及内部控制信号的上升和下降的设置。

公开(公告)号：US20090237588A1

公开(公告)日：2009-09-24

申请号：US12407056

申请日：2009-03-19

申请人： Yuuichi Takenaka ,  Shinji Yasukawa ,  Yukihide Ode

发明人： Yuuichi Takenaka ,  Shinji Yasukawa ,  Yukihide Ode

IPC分类号： G02F1/1333

CPC分类号： G02F1/133308 ,  G02F2001/13332

摘要： An object of the present invention is to provide a technology which makes it possible for the heat from parts having high heat emission mounted on a printed circuit board provided between an upper frame member and a side of the liquid crystal display panel or the backlight to be released efficiently in liquid crystal display devices where the above described parts are mounted. The present invention provides a liquid crystal display device, having: a liquid crystal display panel; a number of flexible wiring boards connected to the above described liquid crystal display panel; a first drive circuit and a second drive circuit provided on the above described flexible wiring boards or the above described liquid crystal display panel; a printed circuit board having wires for transmitting an external signal to the above described first drive circuit and second drive circuit and connected to the above described flexible wiring boards; a semiconductor device mounted on the above described printed circuit board; and an upper frame member made of a metal which covers an outer periphery portion of the above described liquid crystal display panel and the above described printed circuit board, wherein a heat conducting member having heat conductance is provided on the surface of the above described printed circuit board which faces the above described upper frame member, and the above described heat conducting member makes contact with the above described upper frame member.

摘要翻译： 本发明的目的是提供一种技术，其使得可以将安装在设置在液晶显示面板或背光源的上部框架构件和侧面之间的印刷电路板上的具有高散热的部件的热量 在安装上述部件的液晶显示装置中有效地释放。 本发明提供一种液晶显示装置，具有：液晶显示面板; 连接到上述液晶显示面板的多个柔性布线板; 设置在上述柔性布线板或上述液晶显示面板上的第一驱动电路和第二驱动电路; 具有用于将外部信号发送到上述第一驱动电路和第二驱动电路并连接到上述柔性布线板的布线的印刷电路板; 安装在上述印刷电路板上的半导体器件; 以及覆盖上述液晶显示面板的外周部分和上述印刷电路板的由金属构成的上框架构件，其中具有导热性的导热构件设置在上述印刷电路的表面上 面对上述上框架构件的板，并且上述导热构件与上述上框架构件接触。

公开(公告)号：US20080273001A1

公开(公告)日：2008-11-06

申请号：US12216093

申请日：2008-06-30

申请人： Haruhisa Okumura ,  Yukihide Ode

发明人： Haruhisa Okumura ,  Yukihide Ode

IPC分类号： G09G3/36

CPC分类号： H03K19/00384 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0289 ,  H03K19/018571

摘要： A display device includes a pixel driver circuit. Each of level converter circuits in the pixel driver circuit has an input terminal supplied with a signal swinging between a first voltage and a second voltage lower than the first voltage; a first first-conductivity-type transistor having a gate electrode coupled to the input terminal, and a source region coupled to a reference voltage; a second second-conductivity-type transistor having a gate electrode coupled to a drain region of the first transistor, a source region-coupled to a power supply, and a drain region coupled to an output terminal; one circuit element among a diode, a resistor and a fourth second-conductivity-type transistor, coupled between the gate electrode of the second transistor and the power supply; a third first-conductivity-type transistor having a source region coupled to the input terminal, a drain region coupled to the output terminal, and a gate electrode supplied with a do voltage.

摘要翻译： 显示装置包括像素驱动电路。 像素驱动电路中的每个电平转换器电路的输入端被提供有在第一电压和低于第一电压的第二电压之间摆动的信号; 第一第一导电型晶体管，其具有耦合到输入端子的栅极电极和耦合到参考电压的源极区域; 第二第二导电型晶体管，其具有耦合到所述第一晶体管的漏极区的栅极电极，耦合到电源的源极区域和耦合到输出端子的漏极区域; 耦合在第二晶体管的栅电极和电源之间的二极管，电阻器和第四第二导电型晶体管中的一个电路元件; 具有耦合到输入端子的源极区域的第三第一导电型晶体管，耦合到输出端子的漏极区域和提供有电压的栅极电极。