公开(公告)号：US20210327649A1

公开(公告)日：2021-10-21

申请号：US17205069

申请日：2021-03-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi MURAMATSU ,  Ken TOMINAGA

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/008 ,  H01G4/232 ,  H01G4/12

Abstract: A multilayer ceramic capacitor includes an external electrode including an underlying electrode layer, a lower plating layer on the underlying electrode layer at a first end surface and a second end surface, and an upper plating layer on the lower plating layer. The underlying electrode layer is a thin film electrode including at least one selected from Ni, Cr, Cu, and Ti. The lower plating layer is a Cu plating layer including a lower layer region located closer to the multilayer body and an upper layer region located between the lower layer region and the upper plating layer, and the Cu plating layer in the lower layer region has a metal grain diameter smaller than that of the Cu plating layer located in the upper layer region.

公开(公告)号：US20200234887A1

公开(公告)日：2020-07-23

申请号：US16747632

申请日：2020-01-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi MURAMATSU

IPC: H01G4/30 ,  H01G4/12 ,  H01G4/012 ,  H01G2/02

Abstract: A multilayer ceramic capacitor includes a stacked body and external electrodes. The stacked body includes stacked dielectric layers and internal electrodes. The external electrodes are disposed on lateral surfaces of the stacked body and are connected to the internal electrodes. The dielectric layers include outer layer portions and an effective layer portion. Each outer layer portion is adjacent to a corresponding main surface of the stacked body. Each outer layer portion is a dielectric layer located between a corresponding main surface and an internal electrode closest to the main surface. A ratio of a dimension of the effective layer portion in a stacking direction to a dimension of the stacked body in the stacking direction is not less than about 53% and not more than about 83%.