公开(公告)号：US20230154685A1

公开(公告)日：2023-05-18

申请号：US17974701

申请日：2022-10-27

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kotaro KISHI ,  Satoshi MURAMATSU

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/224

CPC classification number: H01G4/30 ,  H01G4/012 ,  H01G4/1227 ,  H01G4/224 ,  H01G4/008

Abstract: A multilayer ceramic capacitor includes a multilayer body having a dimensional relationship of the dimension in the width direction is greater than the dimension in the length direction which is greater than the dimension in the height direction. The dimension in the width direction of a third surface portion of a first external electrode is smaller than the dimension in the width direction of a first surface portion. The dimension in the width direction of an eighth surface portion of a second external electrode is smaller than the dimension in the width direction of a sixth surface portion. The dimensions in the height direction of a fourth surface portion and a fifth surface portion of the first external electrode are smaller than the dimension in the height direction of the first surface portion.

公开(公告)号：US20230018369A1

公开(公告)日：2023-01-19

申请号：US17848434

申请日：2022-06-24

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Ken TOMINAGA ,  Satoshi MURAMATSU

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/008 ,  H01G4/12 ,  H01G2/06

Abstract: A multilayer ceramic electronic component includes a multilayer body including ceramic layers that are laminated, first and second internal electrode layers respectively on the ceramic layers and exposed to first and second end surfaces, first and second external electrodes respectively connected to the first and second internal electrode layers. The first and second external electrodes include a base electrode layer including at least one of Ni, Cr, Cu, or Ti and a plating layer including lower, middle, and upper layer plating layers. A particle diameter of a metal included in the lower layer plating layer is larger than a particle diameter of a metal included in the middle layer plating layer.

公开(公告)号：US20220165503A1

公开(公告)日：2022-05-26

申请号：US17665758

申请日：2022-02-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi MURAMATSU

IPC: H01G4/30 ,  H01G2/02 ,  H01G4/012 ,  H01G4/12

Abstract: A multilayer ceramic capacitor includes a stacked body and external electrodes. The stacked body includes stacked dielectric layers and internal electrodes. The external electrodes are disposed on lateral surfaces of the stacked body and are connected to the internal electrodes. The dielectric layers include outer layer portions and an effective layer portion. Each outer layer portion is adjacent to a corresponding main surface of the stacked body. Each outer layer portion is a dielectric layer located between a corresponding main surface and an internal electrode closest to the main surface. A ratio of a dimension of the effective layer portion in a stacking direction to a dimension of the stacked body in the stacking direction is not less than about 53% and not more than about 83%.

公开(公告)号：US20210225590A1

公开(公告)日：2021-07-22

申请号：US17221857

申请日：2021-04-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi MURAMATSU ,  Masatoshi YANAGIHARA ,  Akitaka DOI

IPC: H01G4/008 ,  H01G4/30 ,  H01G4/232

Abstract: An electronic component includes a multilayer body including inner electrodes and dielectric layers alternately stacked, and an outer electrode electrically connected to the inner electrodes. The multilayer body includes first and second main surfaces opposite to each other in a stacking direction, first and second side surfaces opposite to each other in a width direction, and first and second end surfaces opposite to each other in a length direction. The outer electrode includes first outer electrodes disposed on the first and second end surfaces, and at least one second outer electrode disposed on at least one of the first and second side surfaces. The at least one second outer electrode is directly connected to the inner electrodes at positions spaced away from the at least one of the first or second side surface toward the inside of the multilayer body.

公开(公告)号：US20210183570A1

公开(公告)日：2021-06-17

申请号：US17118667

申请日：2020-12-11

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Suguru NAKANO ,  Satoshi MURAMATSU ,  Risa HOJO ,  Yoshiyuki NOMURA

IPC: H01G4/12 ,  H01G4/012 ,  H01G4/008 ,  H01G4/30

Abstract: A multilayer ceramic capacitor includes: a laminate including dielectric layers and internal electrode layers; and external electrodes on the main surfaces of the laminate. The laminate further includes a first via conductor, a second via conductor, a third via conductor, and a fourth via conductor that connect the internal electrode layers and the external electrodes. The external electrodes include first external electrodes, second external electrodes, third external electrodes, and fourth external electrodes, each connected to the respective end surfaces of the via conductor. Each of the external electrodes does not extend to the side surfaces of the laminate. A ratio W/L of a dimension W in the width direction of the multilayer ceramic capacitor to a dimension L in the length direction of the multilayer ceramic capacitor is about 0.85 or more and about 1 or less. The dimension L in the length direction of the multilayer ceramic capacitor is about 750 μm or smaller.

公开(公告)号：US20200234883A1

公开(公告)日：2020-07-23

申请号：US16747633

申请日：2020-01-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi MURAMATSU

IPC: H01G4/248 ,  H01G4/30 ,  H01G4/012 ,  H01G4/232 ,  H01G4/12

Abstract: A multilayer ceramic capacitor includes a stacked body and external electrodes. The stacked body includes stacked dielectric layers and internal electrodes. The external electrodes are disposed on lateral surfaces of the stacked body and are connected to the internal electrodes. A ratio of min to max is not less than about 36% and not more than about 90%, where A1, A2, A3, and A4 respectively denote the surface areas of first, second, third, and fourth external electrodes that are located on the first or second main surface of the stacked body.

公开(公告)号：US20240153712A1

公开(公告)日：2024-05-09

申请号：US18410081

申请日：2024-01-11

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi MURAMATSU ,  Ken TOMINAGA

IPC: H01G4/30 ,  H01G4/008 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232

CPC classification number: H01G4/30 ,  H01G4/008 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232

Abstract: A multilayer ceramic capacitor includes an external electrode including an underlying electrode layer, a lower plating layer on the underlying electrode layer at a first end surface and a second end surface, and an upper plating layer on the lower plating layer. The underlying electrode layer is a thin film electrode including at least one selected from Ni, Cr, Cu, and Ti. The lower plating layer is a Cu plating layer including a lower layer region located closer to the multilayer body and an upper layer region located between the lower layer region and the upper plating layer, and the Cu plating layer in the lower layer region has a metal grain diameter smaller than that of the Cu plating layer located in the upper layer region.

公开(公告)号：US20230352242A1

公开(公告)日：2023-11-02

申请号：US18212809

申请日：2023-06-22

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Suguru NAKANO ,  Satoshi MURAMATSU ,  Risa HOJO ,  Yoshiyuki NOMURA

IPC: H01G4/30 ,  H01G4/012 ,  H01G2/06 ,  H01G4/008 ,  H01G4/12

CPC classification number: H01G4/30 ,  H01G4/012 ,  H01G2/065 ,  H01G4/008 ,  H01G4/1218

Abstract: A multilayer ceramic capacitor includes a laminate including dielectric layers and internal electrode layers, and first and second external electrodes on surfaces of the laminate. The laminate includes first and second main surfaces oppose each other in a lamination direction, first and second side surfaces oppose each other in a length direction perpendicular or substantially perpendicular to the lamination direction, and third and fourth side surfaces oppose each other in a width direction perpendicular or substantially perpendicular to the lamination direction and the length direction. A length ratio EB1/EA1 of the first external electrode wrapping around to main surfaces of the laminate is about 0 or more and about 0.5 or less. A length ratio EB2/EA2 of the second external electrode wrapping around to the main surfaces of the laminate is about 0 or more and about 0.5 or less.

公开(公告)号：US20230298818A1

公开(公告)日：2023-09-21

申请号：US18105301

申请日：2023-02-03

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kotaro KISHI ,  Satoshi MURAMATSU

IPC: H01G4/12 ,  H01G4/30 ,  H01G4/232

CPC classification number: H01G4/12 ,  H01G4/30 ,  H01G4/232

Abstract: A multilayer ceramic capacitor includes a multilayer body in which a dimension in a width direction >a dimension in a length direction >a dimension in a height direction is satisfied. A dimension in the length direction of each of lateral surface exposed portions is about 10% or more and about 44% or less with respect to the dimension in the length direction. A dimension of the external electrode in the length direction is about 17% or more and about 48% or less with respect to the dimension in the length direction.

公开(公告)号：US20220208459A1

公开(公告)日：2022-06-30

申请号：US17532268

申请日：2021-11-22

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi MURAMATSU

IPC: H01G4/232 ,  H01G4/30 ,  H01G4/248 ,  H01G4/12

Abstract: A multilayer ceramic capacitor includes a multilayer body including layered ceramic layers and internal electrode layers, and an external electrode on a side surface of the multilayer body and connected to the internal electrode layers. A recess is provided in a surface of the external electrode on one side of opposing main surfaces of the multilayer ceramic capacitor.