公开(公告)号：US20160055093A1

公开(公告)日：2016-02-25

申请号：US14462763

申请日：2014-08-19

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  George Patsilaras ,  Bohuslav Rychlik

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F12/0866 ,  G06F12/0886 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/401 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for implementing a cache memory access requests for data smaller than a cache line and eliminating overfetching from a main memory by writing supplemental data to the unfilled portions of the cache line. A cache memory controller may receive a cache memory access request with a supplemental write command for data smaller than a cache line. The cache memory controller may write supplemental to the portions of the cache line not filled by the data in response to a write cache memory access request or a cache miss during a read cache memory access request. In the event of a cache miss, the cache memory controller may retrieve the data from the main memory, excluding any overfetch data, and write the data and the supplemental data to the cache line. Eliminating overfetching reduces bandwidth and power required to retrieved data from main memory.

Abstract translation: 方面包括用于对小于高速缓存线的数据实现高速缓冲存储器访问请求的计算设备，系统和方法，并且通过将补充数据写入到高速缓存行的未填充部分来消除从主存储器的超时。 高速缓存存储器控制器可以接收具有小于高速缓存线的数据的补充写入命令的高速缓存存储器访问请求。 高速缓冲存储器控制器可以在读取高速缓存存储器访问请求期间响应于写入高速缓存存储器访问请求或高速缓存未命中而对未被数据填充的高速缓存行的部分进行补充。 在高速缓存未命中的情况下，高速缓存存储器控制器可以从主存储器检索数据，排除任何过采取数据，并将数据和补充数据写入高速缓存行。 消除过载减少从主存储器检索数据所需的带宽和功率。

公开(公告)号：US20160041905A1

公开(公告)日：2016-02-11

申请号：US14451639

申请日：2014-08-05

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  George Patsilaras ,  Bohuslav Rychlik

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F12/0802 ,  G06F12/0886 ,  G06F2212/1021 ,  G06F2212/401 ,  G06F2212/45 ,  G06F2212/608

Abstract: Methods, devices, and non-transitory process-readable storage media for compacting data within cache lines of a cache. An aspect method may include identifying, by a processor of the computing device, a base address (e.g., a physical or virtual cache address) for a first data segment, identifying a data size (e.g., based on a compression ratio) for the first data segment, obtaining a base offset based on the identified data size and the base address of the first data segment, and calculating an offset address by offsetting the base address with the obtained base offset, wherein the calculated offset address is associated with a second data segment. In some aspects, the method may include identifying a parity value for the first data segment based on the base address and obtaining the base offset by performing a lookup on a stored table using the identified data size and identified parity value.