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    Migration of data to register file cache
    7.
    发明授权
    Migration of data to register file cache 有权

    公开(公告)号：US09858194B2

    公开(公告)日：2018-01-02

    申请号：US15438000

    申请日：2017-02-21

    申请人： Imagination Technologies Limited

    发明人： Hugh Jackson ,  Anand Khot

    IPC分类号： G06F12/0875 ,  G06F9/30 ,  G06F9/38

    CPC分类号： G06F12/0875 ,  G06F9/30101 ,  G06F9/30138 ,  G06F9/384 ,  G06F2212/45 ,  G06F2212/452

    摘要： Methods and migration units for use in out-of-order processors for migrating data to register file caches associated with functional units of the processor to satisfy register read operations. The migration unit receives register read operations to be executed for a particular functional unit. The migration unit reviews entries in a register renaming table to determine if the particular functional unit has recently accessed the source register and thus is likely to comprise an entry for the source register in its register file cache. In particular, the register renaming table comprises entries for physical registers that indicate what functional units have accessed the physical register. If the particular functional unit has not accessed the particular physical register the migration unit migrates data to the register file cache associated with the particular functional unit.

    IN-MEMORY INTERCONNECT PROTOCOL CONFIGURATION REGISTERS
    9.
    发明申请
    IN-MEMORY INTERCONNECT PROTOCOL CONFIGURATION REGISTERS 有权

    公开(公告)号：US20170123987A1

    公开(公告)日：2017-05-04

    申请号：US14928981

    申请日：2015-10-30

    申请人： Advanced Micro Devices, Inc.

    发明人： Kevin Y. Cheng ,  David A. Roberts

    IPC分类号： G06F12/08 ,  G06F13/42

    CPC分类号： G06F12/0862 ,  G06F9/4401 ,  G06F13/42 ,  G06F15/7821 ,  G06F2212/1024 ,  G06F2212/45

    摘要： Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. Interconnect protocol configuration registers which are used during a startup routine may be prefetched into the host's cache to make the startup routine more efficient. The interconnect protocol configuration registers for various interconnect protocols may include one or more of device capability tables, memory-side statistics (e.g., to support two-level memory data mapping decisions), advanced memory and interconnect features such as repair resources and routing tables, prefetching hints, error correcting code (ECC) bits, lists of device capabilities, set and store base address, capability, device ID, status, configuration, capabilities, and other settings.

    MEMORY CONTROLLERS EMPLOYING MEMORY CAPACITY AND/OR BANDWIDTH COMPRESSION WITH NEXT READ ADDRESS PREFETCHING, AND RELATED PROCESSOR-BASED SYSTEMS AND METHODS
    10.
    发明申请
    MEMORY CONTROLLERS EMPLOYING MEMORY CAPACITY AND/OR BANDWIDTH COMPRESSION WITH NEXT READ ADDRESS PREFETCHING, AND RELATED PROCESSOR-BASED SYSTEMS AND METHODS 有权
    使用下一个读取地址前缀的存储器容量和/或带宽压缩的存储器控​​制器和相关的基于处理器的系统和方法

    公开(公告)号：US20150339237A1

    公开(公告)日：2015-11-26

    申请号：US14716108

    申请日：2015-05-19

    申请人： QUALCOMM Incorporated

    发明人： Mattheus Cornelis Antonius Adrianus Heddes ,  Natarajan Vaidhyanathan ,  Colin Beaton Verrilli

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0875 ,  G06F12/0246 ,  G06F12/0862 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/1056 ,  G06F2212/251 ,  G06F2212/401 ,  G06F2212/45 ,  G06F2212/602 ,  H03M7/30 ,  Y02D10/13

    摘要： Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods are disclosed. In certain aspects, memory controllers are employed that can provide memory capacity compression. In certain aspects disclosed herein, a next read address prefetching scheme can be used by a memory controller to speculatively prefetch data from system memory at another address beyond the currently accessed address. Thus, when memory data is addressed in the compressed memory, if the next read address is stored in metadata associated with the memory block at the accessed address, the memory data at the next read address can be prefetched by the memory controller to be available in case a subsequent read operation issued by a central processing unit (CPU) has been prefetched by the memory controller.

    摘要翻译： 公开了采用存储器容量和/或带有下一个读取地址预取的带宽压缩的存储器控​​制器以及相关的基于处理器的系统和方法。 在某些方面，采用可提供存储容量压缩的存储器控​​制器。 在本文公开的某些方面，存储器控制器可以使用下一个读取地址预取方案来在超出当前访问的地址的另一地址上推测性地从系统存储器预取数据。 因此，当在压缩存储器中寻址存储器数据时，如果下一个读取地址存储在与访问地址处的存储器块相关联的元数据中，则下一个读取地址的存储器数据可以被存储器控制器预取为可用于 已经由存储器控制器预取了由中央处理单元（CPU）发出的后续读取操作的情况。