公开(公告)号：US20250119535A1

公开(公告)日：2025-04-10

申请号：US18882291

申请日：2024-09-11

Applicant: QUALCOMM Incorporated

Inventor： Yan Zhang ,  Vadim Seregin ,  Hongtao Wang ,  Zhi Zhang ,  Chun-Chi Chen ,  Han Huang ,  Marta Karczewicz

IPC: H04N19/109 ,  H04N19/176 ,  H04N19/44 ,  H04N19/463 ,  H04N19/513 ,  H04N19/573

Abstract: Example devices, methods, and computer-readable media are described. An example method includes determining to decode a current block of the video data using a merge mode. The example method includes determining, for the current block, to apply local illumination compensation (LIC). The example method includes determining, for the current block, to apply decoder side motion vector refinement (DMVR). The example method includes decoding the current block based on applying LIC and applying DMVR.

公开(公告)号：US12250395B2

公开(公告)日：2025-03-11

申请号：US18057500

申请日：2022-11-21

Applicant: QUALCOMM Incorporated

Inventor： Chun-Chi Chen ,  Han Huang ,  Zhi Zhang ,  Yao-Jen Chang ,  Yan Zhang ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/503 ,  H04N19/105 ,  H04N19/109 ,  H04N19/132 ,  H04N19/159 ,  H04N19/172 ,  H04N19/176

Abstract: A video encoder and video decoder may determine to enable or disable a template-based inter prediction technique based on whether reference picture resampling or weighted prediction are used. A video encoder and video decoder may determine that a reference picture resampling mode is enabled. determine not to apply a template-based inter prediction technique to the video data based on the reference picture resampling mode being enabled, and code the video data using inter prediction without applying the template-based inter prediction technique.

公开(公告)号：US20240388719A1

公开(公告)日：2024-11-21

申请号：US18657110

申请日：2024-05-07

Applicant: QUALCOMM Incorporated

Inventor： Yan Zhang ,  Han Huang ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/157 ,  H04N19/105 ,  H04N19/176 ,  H04N19/46

Abstract: A video encoder and video decoder are configured to code a block of video data using a merge candidate list that includes one or more bi-predicted merge candidates, determine to apply only one of a decoder side motion vector refinement (DMVR) mode or a local illumination compensation (LIC) mode to the block of video data, and apply one of the DMVR mode or the LIC mode to the block of video data based on the determination.

公开(公告)号：US20240137524A1

公开(公告)日：2024-04-25

申请号：US18481590

申请日：2023-10-05

Applicant: QUALCOMM Incorporated

Inventor： Yan Zhang ,  Han Huang ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/149 ,  H04N19/136 ,  H04N19/176 ,  H04N19/184

CPC classification number: H04N19/149 ,  H04N19/136 ,  H04N19/176 ,  H04N19/184

Abstract: An example device for coding video data includes memory configured to store the video data and one or more processors communicatively coupled to the memory. The one or more processors are configured to reduce a bit length of one or more input variables for a linear regression operation to generate one or more reduced bit length input variables, the input variables including at least one of a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing a number of subblocks. The one or more processors are configured to perform the linear regression operation and derive an affine motion model based on the performing the linear regression on the one or more reduced bit length input variables. The one or more processors are configured to code a current block of the video data based on the affine motion model.

公开(公告)号：US20240089492A1

公开(公告)日：2024-03-14

申请号：US18514588

申请日：2023-11-20

Applicant: QUALCOMM Incorporated

Inventor： Yan Zhang ,  Zhi Zhang ,  Vadim Seregin ,  Marta Karczewicz ,  Chun-Chi Chen

IPC: H04N19/52 ,  H04N19/105 ,  H04N19/55 ,  H04N19/70

CPC classification number: H04N19/52 ,  H04N19/105 ,  H04N19/55 ,  H04N19/70 ,  H04N19/176

Abstract: An example device includes memory configured to store the video data and one or more processors implemented in circuitry and communicatively coupled to the memory. The one or more processors are configured to determine at least one of a temporal candidate or a history-based candidate and determine at least one non-adjacent candidate, wherein the at least one non-adjacent candidate is from a unit that is not adjacent to a current prediction unit (PU). The one or more processors are configured to determine an advanced motion vector predictor (AMVP) candidate list including the at least one of the temporal candidate or the history-based candidate and the at least one non-adjacent candidate. The at least one non-adjacent candidate is added to the AMVP candidate list after the temporal candidate or before the history-based candidate. The one or more processors are configured to code the current PU based on the AMVP candidate list.

公开(公告)号：US20240022729A1

公开(公告)日：2024-01-18

申请号：US18351342

申请日：2023-07-12

Applicant: QUALCOMM Incorporated

Inventor： Han Huang ,  Yan Zhang ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/137 ,  H04N19/80 ,  H04N19/176 ,  H04N19/70

CPC classification number: H04N19/137 ,  H04N19/80 ,  H04N19/176 ,  H04N19/70

Abstract: An example device includes one or more processors configured determine a plurality of subblocks for a current block of video data. For each subblock, the one or more processors (a) generate initial motion vectors for a first prediction direction and a second prediction direction according to an affine motion model, and (b) determine, based on the initial motion vectors, a subblock bilateral matching cost for each respective offset among a plurality of offsets. For each respective offset, the one or more processors determine a respective summation of subblock bilateral matching costs. The one or more processors determine a lowest summation of subblock bilateral matching costs. The one or more processors select an offset associated with the lowest summation of subblock bilateral matching costs. The one or more processors modify the affine motion model based on the selected offset and code the current block based on the modified affine motion model.

公开(公告)号：US11792412B2

公开(公告)日：2023-10-17

申请号：US17230823

申请日：2021-04-14

Applicant: QUALCOMM Incorporated

Inventor： Dmytro Rusanovskyy ,  Yan Zhang ,  Marta Karczewicz

IPC: H04N19/186 ,  H04N19/117 ,  H04N19/174 ,  H04N19/184

CPC classification number: H04N19/186 ,  H04N19/117 ,  H04N19/174 ,  H04N19/184

Abstract: Systems and techniques are described herein for processing video data. For example, a process can include obtaining a video bitstream, the video bitstream including adaptive loop filter (ALF) data. The process can further include determining a value of an ALF chroma filter signal flag from the ALF data, the value of the ALF chroma filter signal flag indicating whether chroma ALF filter data is signaled in the video bitstream. The process can further include processing at least a portion of a slice of video data based on the value of the ALF chroma filter signal flag.

公开(公告)号：US11582475B2

公开(公告)日：2023-02-14

申请号：US17028064

申请日：2020-09-22

Applicant: QUALCOMM Incorporated

Inventor： Dmytro Rusanovskyy ,  Marta Karczewicz ,  Yan Zhang

IPC: H04N19/513 ,  H04N19/159 ,  H04N19/176 ,  H04N19/56

Abstract: Systems, methods, and computer-readable media are provided for updating history-based motion vector tables. In some examples, a method can include obtaining one or more blocks of video data; determining a first motion vector derived from a first control point of a block of the one or more blocks, the block being coded using an affine motion mode; determining a second motion vector derived from a second control point of the block; based on the first motion vector and the second motion vector, estimating a third motion vector for a predetermined location within the block; and populating a history-based motion vector predictor (HMVP) table with the third motion vector.

公开(公告)号：US11375212B2

公开(公告)日：2022-06-28

申请号：US17231935

申请日：2021-04-15

Applicant: QUALCOMM Incorporated

Inventor： Dmytro Rusanovskyy ,  Yan Zhang ,  Marta Karczewicz

IPC: H04N19/186 ,  H04N19/103 ,  H04N19/132 ,  H04N19/136 ,  H04N19/176 ,  H04N19/70

Abstract: Systems and techniques are described herein for processing video data. In some examples, a process is described that can include obtaining at least one block of video data and predicting one or more video samples for the at least one block. The process can include obtaining a dynamic range adjustment (DRA) syntax element from the video data. In some cases, the DRA syntax element includes an indication associated with a plurality of DRA modes for the video data. The process can include processing the one or more video samples for the at least one block using a DRA mode based on the indication of the DRA syntax element.

公开(公告)号：US11336893B2

公开(公告)日：2022-05-17

申请号：US17142157

申请日：2021-01-05

Applicant: QUALCOMM Incorporated

Inventor： Dmytro Rusanovskyy ,  Yan Zhang ,  Marta Karczewicz

IPC: H04N19/13 ,  H04N19/91 ,  H04N19/42 ,  H04N19/176

Abstract: An example device for coding video data includes a memory configured to store video data; and one or more processors implemented in circuitry and configured to: determine a size of a dimension of a current block of the video data; calculate a context for entropy coding a last significant coefficient coordinate along the dimension, wherein to calculate the context, the one or more processors are configured to: calculate a context shift value according to ((log 2TrafoSize+1)>>2) >’ represents a bitwise right shift operator, and ‘