公开(公告)号：US5608731A

公开(公告)日：1997-03-04

申请号：US414502

申请日：1995-03-31

Applicant: Daniel C. Upp ,  Dan H. Wolaver

Inventor： Daniel C. Upp ,  Dan H. Wolaver

IPC: H04J3/06 ,  H04L12/56 ,  H04Q11/04 ,  H04L7/08

CPC classification number: H04J3/0632 ,  H04Q11/0478 ,  H04L2012/5652 ,  H04L2012/5674

Abstract: An SRTS clock recovery apparatus and method are provided. The apparatus broadly includes a controllable destination node clock generator such as a digitally controllable oscillator, a block for generating a local RTS-related value from the destination node clock and the system reference clock, and a comparator which compares the incoming RTS-related value to the local RTS related value to provide a feedback error or control signal which is used to adjust the controllable clock generator. If desired, a filter which filters the error signal can be provided in the loop. With the feedback loop as provided, when the destination node clock is faster than the source clock, the error signal will cause the destination node clock to slow, and vice versa.

Abstract translation: 提供了一种SRTS时钟恢复装置和方法。 该装置广泛地包括可控目的地节点时钟发生器，例如数字可控振荡器，用于从目的地节点时钟和系统参考时钟产生本地RTS相关值的块，以及将进入的RTS相关值与 本地RTS相关值提供反馈误差或控制信号，用于调节可控时钟发生器。 如果需要，可以在循环中提供过滤误差信号的滤波器。 使用所提供的反馈回路，当目的地节点时钟比源时钟快时，误差信号将导致目的地节点时钟减慢，反之亦然。

公开(公告)号：US5568060A

公开(公告)日：1996-10-22

申请号：US504568

申请日：1995-07-20

Applicant: William G. Bartholomay ,  Eugene L. Parrella ,  Daniel C. Upp ,  Mikio S. Ichiba

Inventor： William G. Bartholomay ,  Eugene L. Parrella ,  Daniel C. Upp ,  Mikio S. Ichiba

IPC: G06F1/18 ,  G06F3/00 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/094

CPC classification number: H03K19/018557 ,  H03K19/09429

Abstract: Circuit board insertion circuitry is used in conjunction with a staggered electrical connector. The insertion circuitry includes an isolated circuit which receives a high system voltage upon first stage contact between the card and a high voltage bus, and uses that high system voltage to tristate the output of a transceiver on the circuit board prior to second stage contact being made between the transceiver and the backplane data bus. Override circuitry for overriding the tristating effects of the isolating circuit are provided such that when the bias circuit which controls the transceiver output is properly powered, the bias circuit will control the transceiver output, and not the isolated circuit. Additional circuitry which isolates the circuit board so that a power fault on the board will not impact other boards on the backplane is also provided. The additional circuitry preferably includes a relative large resistor and a Schottky diode which are provided in parallel between a 5 V bus and the protection diodes of the transceiver.

Abstract translation: 电路板插入电路与交错的电连接器一起使用。 插入电路包括隔离电路，其在卡和高电压总线之间的第一级接触时接收高系统电压，并且在第二级接触之前使用该高系统电压将电路板上的收发器的输出三态化 在收发器和背板数据总线之间。 提供用于覆盖隔离电路的三态效应的覆盖电路，使得当控制收发器输出的偏置电路被适当地供电时，偏置电路将控制收发器输出，而不是隔离电路。 还提供了隔离电路板以使电路板上的电源故障不会影响背板上的其他电路板的附加电路。 附加电路优选地包括并联设置在5V总线和收发器的保护二极管之间的相对较大的电阻器和肖特基二极管。

公开(公告)号：US5142529A

公开(公告)日：1992-08-25

申请号：US559636

申请日：1990-07-27

Applicant: Bidyut Parruck ,  Daniel C. Upp

Inventor： Bidyut Parruck ,  Daniel C. Upp

IPC: G06F5/10 ,  G06F5/12 ,  H04J3/06 ,  H04J3/07 ,  H04J3/16 ,  H04L25/05

CPC classification number: G06F5/12 ,  H04J3/0623 ,  H04J3/076 ,  H04J3/1611 ,  H04L25/05 ,  G06F2205/123 ,  Y10S370/907

Abstract: An apparatus and method for transferring a data payload (SPE) from a first substantially SONET signal into a second substantially SONET signal of different frequency is provided. The apparatus has: a circuit for extracting the SPE from the first SONET signal and sending the bytes of the SPE, according to a first clock, to a FIFO for storage; a circuit for obtaining the SPE bytes from the FIFO according to a second clock, for building the SPE into the second substantially SONET signal; and a circuit for comparing the relative byte phases of the first and second clocks. The byte phase comparison circuit serves two functions. In order to avoid read/write conflicts in the FIFO, it generates and sends a signal to the extracting circuit which causes the extracting circuit to change the byte phase (i.e. timing) at which bytes are sent to the FIFO. Also, in order to adjust the SPE for frequency differences between the first and second substantially SONET signals, the byte phase comparison circuits sends a signal to the circuit which builds the second substantially SONET signal when the two SONET signals have slipped a byte relative to each other. In response thereto, the second substantially SONET signal building circuit generates a negative or positive stuff.

Abstract translation: 提供了一种用于将数据有效载荷（SPE）从第一基本SONET信号传送到不同频率的第二基本SONET信号的装置和方法。 该装置具有：用于从第一SONET信号提取SPE并根据第一时钟将SPE的字节发送到FIFO以存储的电路; 用于根据第二时钟从FIFO获取SPE字节的电路，用于将SPE构建成第二基本SONET信号; 以及用于比较第一和第二时钟的相对字节相位的电路。 字节相位比较电路有两个功能。 为了避免FIFO中的读/写冲突，它产生并发送一个信号到提取电路，使得提取电路将字节发送到FIFO的字节相位（即定时）改变。 此外，为了调整第一和第二基本SONET信号之间的频率差的SPE，当两个SONET信号相对于每个SONET信号滑过一个字节时，字节相位比较电路向建立第二基本SONET信号的电路发送信号 其他。 响应于此，第二基本上SONET信号建立电路产生负的或正的东西。

公开(公告)号：US5119326A

公开(公告)日：1992-06-02

申请号：US447093

申请日：1989-12-06

Applicant: William T. Cochran ,  Joseph R. Yudichak ,  Daniel C. Upp

Inventor： William T. Cochran ,  Joseph R. Yudichak ,  Daniel C. Upp

IPC: H03H15/00 ,  H03K5/00 ,  H03K5/13 ,  H04B3/04 ,  H04L25/04

CPC classification number: H03K5/13 ,  H03K5/133 ,  H03K2005/00045 ,  H03K2005/00097

Abstract: The transversal filter has a plurality of variable delay lines each having multiple voltage controlled delay stages in series, with one of the variable delay lines having a clock input, and the other variable delay lines having data signal inputs. A phase comparator is coupled to the output of two non-adjacent stages of the variable delay lines having the clock input. A feedback circuit is coupled to the comparator and provides voltage signals to the voltage controlled delay stages of all of the variable dealy lines, such that adjacent stages in a particular delay line are delayed in time equal fractions of a clock cycle from each other, and so that all delay lines are running on the same clock. A voltage weighting circuit is provided for shaping the voltage outputs of the data signal variable delay lines and the weighting circuit is coupled to the delay line stages by switches which are activated when a data signal is propagated through a delay line stage. Where positive pulse, zero pulse, and negative pulse inputs are provided to the transversal filter along with a clock signal, and where the delay lines of the transversal filter have four or more active stages, a substantially raised cosine B3ZS encoded waveform which can be transmitted over a coaxial cable of up to forty hundred fifty feet in length without requiring line build-out can be provided from an incoming B3ZS encoded DS3 signal.

Abstract translation: 横向滤波器具有多个可变延迟线，每条可变延迟线具有串联的多个电压控制延迟级，其中一个可变延迟线具有时钟输入，而其它可变延迟线具有数据信号输入。 相位比较器耦合到具有时钟输入的可变延迟线的两个不相邻级的输出。 反馈电路耦合到比较器，并将电压信号提供给所有可变衰减线的电压控制延迟级，使得特定延迟线中的相邻级在时间上相互延迟等于时钟周期的分数，以及 所以所有的延迟线都在同一个时钟上运行。 提供电压加权电路，用于对数据信号可变延迟线的电压输出进行整形，并且加权电路通过在数据信号通过延迟线级传播时被激活的开关耦合到延迟线级。 其中正脉冲，零脉冲和负脉冲输入与时钟信号一起提供给横向滤波器，并且其中横向滤波器的延迟线具有四个或更多个有源级，可以传输的基本上升余弦B3ZS编码波形 通过长达四十五十英尺长度的同轴电缆，可以从输入的B3ZS编码的DS3信号提供线路建立。

公开(公告)号：US4914429A

公开(公告)日：1990-04-03

申请号：US283173

申请日：1988-12-09

Applicant: Daniel C. Upp

Inventor： Daniel C. Upp

IPC: H04Q3/52 ,  H03K17/693 ,  H04J3/06 ,  H04Q11/04

CPC classification number: H04Q11/04 ,  H03K17/693 ,  H04J3/0685

Abstract: A switching component preferably in integrated circuit form is provided. The switching component has a plurality of inlet and outlet data ports with associated inlet and outlet clock ports, a clock regenerator and a flip-flop for each outlet data port, and a switch matrix for coupling each inlet data port and its associated inlet clock port to any outlet data port and its associated outlet clock port. The clock regeneration means obtains the clock signal exiting the switching core and regenerates the clock signal waveshape. The flip-flop causes data exiting the switching core to be clocked out of the switching component synchronously with its associated regenerated clock signal according to the regenerated clock signal. A plurality of identical switching components can be arranged in a folded Clos arrangement having a plurality of stages to provide a desired switch network of any size. The use of multiple stages is permitted as the clock regeneration means associated with each port prevents signal dispersion and signal clock skew. The passing and switching of clock signals along with the data also permits the switching matrix to simultaneosuly handle lines having different rates, provided that a line of a given rate which is an input to the switching network must be connected to another line of the same rate which is an output of the switching network.

Abstract translation: 提供了一种优选集成电路形式的开关元件。 开关组件具有多个入口和出口数据端口，其具有相关联的入口和出口时钟端口，用于每个出口数据端口的时钟再生器和触发器，以及用于耦合每个入口数据端口及其相关联的入口时钟端口的开关矩阵 到任何出口数据端口及其相关的插座时钟端口。 时钟再生装置获得离开切换核心的时钟信号并再生时钟信号波形。 根据再生的时钟信号，触发器使得离开开关核心的数据与其相关联的再生时钟信号同步地从开关部件中输出。 多个相同的切换部件可以布置成具有多个级的折叠的Clos布置，以提供任何尺寸的期望的开关网络。 允许使用多级，因为与每个端口相关联的时钟再生装置防止信号色散和信号时钟偏移。 时钟信号与数据的通过和切换也允许交换矩阵同时处理具有不同速率的线路，只要作为交换网络的输入的给定速率的线路必须连接到相同速率的另一条线路 这是交换网络的输出。

公开(公告)号：US4439826A

公开(公告)日：1984-03-27

申请号：US284866

申请日：1981-07-20

Applicant: Alan J. Lawrence ,  Daniel C. Upp

Inventor： Alan J. Lawrence ,  Daniel C. Upp

IPC: H04Q1/24 ,  H04Q11/04 ,  G06F11/00

CPC classification number: H04Q11/0407 ,  H04Q1/245

Abstract: A diagnostic system for a telecommunications system including a digital switching network is controlled via a plurality of data processors. Each of the distributed data processors has a unique address and has diagnostic data stored therein for use in performing diagnostics in the switching network. The switching network includes digital switching elements, each having bidirectional ports for receiving and transmitting digital signals, and each of the bidirectional ports also having a unique address in the network. Diagnostic paths are established under processor control between the digital switching elements and the data processors. Each of the data processors is interconnected to another data processor by connection paths equal in number to the number of bidirectional communication paths originating from such data processor so that the addresses of the data processors are algorithimically related to the addresses of the bidirectional ports interconnected by the diagnostic paths, thereby achieving a simplified and reliable protocol for data transfer from processor to processor.

Abstract translation: 包括数字交换网络的电信系统的诊断系统通过多个数据处理器进行控制。 每个分布式数据处理器具有唯一的地址，并且其中存储有用于在交换网络中执行诊断的诊断数据。 交换网络包括数字交换元件，每个元件具有用于接收和发送数字信号的双向端口，并且每个双向端口在网络中也具有唯一的地址。 在数字开关元件和数据处理器之间的处理器控制下建立诊断路径。 每个数据处理器通过与从这种数据处理器产生的双向通信路径的数目相等的连接路径互连到另一个数据处理器，使得数据处理器的地址在算术上与由 诊断路径，从而实现用于从处理器到处理器的数据传输的简化和可靠的协议。