公开(公告)号：US20190004564A1

公开(公告)日：2019-01-03

申请号：US15573917

申请日：2016-06-14

申请人： GYAN PRAKASH ,  NIDHIR KUMAR

发明人： GYAN PRAKASH ,  NIDHIR KUMAR

IPC分类号： G06F1/12

CPC分类号： G06F1/12 ,  G06F1/04 ,  G06F5/06 ,  G06F5/10 ,  G06F9/30141 ,  G06F9/3869 ,  G06F2205/123 ,  G11C7/10 ,  G11C7/1093 ,  G11C7/22 ,  H03K19/20

摘要： A method and system for cycle accurate data transfer between skewed source synchronous clocks is envisaged. The procedure starts through reset. On reset, both the write and read address registers are set to point to location 0. Source clock is stopped to disable active clock edges to both write and read address registers during the reset procedure. The source clock is subsequently started to deliver active edges w both write and read address registers. On every active source clock edge, data is pushed into the data register based on the location pointed by write address resister. On every skewed active clock edge, data is read from the data register based on the address pointed by read address register. Due to the delayed nature of clock reaching the read address register, write address register increments first and stores data into the data register.

公开(公告)号：US08768889B1

公开(公告)日：2014-07-01

申请号：US10820661

申请日：2004-04-07

申请人： Paul A. Martin

发明人： Paul A. Martin

IPC分类号： G06F7/00

CPC分类号： G06F5/06 ,  G06F2205/064 ,  G06F2205/123

摘要： One embodiment of the present invention provides a system that performs a lock-free update to one or more fields in an existing node in a linked list. To perform the update, the system first obtains a new node to be added to the linked list, wherein other processes do not possess references to the new node and therefore cannot initially access the new node. Next, the system copies a snapshot of the existing node to the new node, and then updates one or more fields in the new node that correspond to the one or more fields in the existing node. Next, in a single atomic operation the system modifies a next pointer of the existing node to point to the new node and also marks the next pointer to indicate that the existing node is deleted. In this way, the new node becomes part of the linked list and the existing node is deleted in a single atomic operation.

摘要翻译： 本发明的一个实施例提供一种对链表中的现有节点中的一个或多个字段执行无锁更新的系统。 为了执行更新，系统首先获得要添加到链表中的新节点，其中其他进程不具有对新节点的引用，因此不能初始地访问新节点。 接下来，系统将现有节点的快照复制到新节点，然后更新新节点中与现有节点中的一个或多个字段对应的一个或多个字段。 接下来，在单个原子操作中，系统修改现有节点的下一个指针以指向新节点，并且还标记下一个指针以指示现有节点被删除。 以这种方式，新节点成为链表的一部分，并且现有节点在单个原子操作中被删除。

公开(公告)号：US20090204755A1

公开(公告)日：2009-08-13

申请号：US12028091

申请日：2008-02-08

申请人： THOMAS BRYAN RUSHWORTH ,  ANGUS RICHARD TELFER

发明人： THOMAS BRYAN RUSHWORTH ,  ANGUS RICHARD TELFER

IPC分类号： G06F12/00

CPC分类号： G06F9/526 ,  G06F5/12 ,  G06F2205/123 ,  G06F2209/521

摘要： A method for accessing cells of a ring buffer by one or more writers, comprising: storing a current writer cell position value in each of a done writer index and a reserved writer index; storing a current reader cell position value in a done reader index; copying the current writer cell position value to an old writer variable of a writer of the one or more writers; assigning a trial next writer cell position value to a new writer variable of the writer; accepting the trial next writer cell position value if the trial next writer cell position value is not equal to the done reader index value; as a single operation, first, accepting the trial next writer cell position value as a next writer cell position value if the reserved writer index value is equal to the old writer variable value, and second, replacing the reserved writer index value with the new writer variable value; writing data by the writer to a cell of the ring buffer indicated by the next writer cell position value; and, when the done writer index value is equal to the old writer variable value, replacing the done writer index value with the new writer variable value; whereby the one or more writers are prevented from simultaneously accessing the cell of the ring buffer. In addition, a method for accessing cells of a ring buffer by one or more readers, comprising: storing a current reader cell position value in each of a done reader index and a reserved reader index; storing a current writer cell position value in a done writer index; copying the current reader cell position value to an old reader variable of a reader of the one or more readers; assigning a trial next reader cell position value to a new reader variable of the reader; accepting the trial next reader cell position value if the old reader variable value is not equal to the done writer index value; as a single operation, first, accepting the trial next reader cell position value as a next reader cell position value if the reserved reader index value is equal to the old reader variable value, and second, replacing the reserved reader index value with the new reader variable value; reading data by the reader from a cell of the ring buffer indicated by the next reader cell position value; and, when the done reader index value is equal to the old reader variable value, replacing the done reader index value with the new reader variable value; whereby the one or more readers are prevented from simultaneously accessing the cell of the ring buffer.

公开(公告)号：US07536428B2

公开(公告)日：2009-05-19

申请号：US11585741

申请日：2006-10-23

申请人： Tahsin Erdogan ,  Adrian Marinescu ,  Dragos C. Sambotin

发明人： Tahsin Erdogan ,  Adrian Marinescu ,  Dragos C. Sambotin

IPC分类号： G06F17/30 ,  G06F17/00 ,  G06F13/00

CPC分类号： G06F5/10 ,  G06F2205/064 ,  G06F2205/106 ,  G06F2205/123 ,  Y10S707/99931 ,  Y10S707/99938 ,  Y10S707/99943 ,  Y10S707/99957

摘要： A method and computing device for providing concurrent read and write access to a linked list of elements is presented. A linked list is provided wherein read access by a reader process and write access by a writer process may occur substantially concurrently. The linked list includes three internal lists for processes to reference elements of the linked list. The linked list also includes an updated indicator. Read access to the linked list is provided to a reader process such that the reader process accesses elements in the linked list according to a read list of the three internal lists. Write access to the linked list is provided to a writer process such that the writer process accesses elements in the linked list according to a write list of the three internal lists.

摘要翻译： 提出了一种用于提供对链接的元素列表的并发读取和写入访问的方法和计算设备。 提供了链接列表，其中由读取器处理的读取访问和写入器进程的写入访问可以基本同时发生。 链表包括三个用于引用链表的元素的进程的内部列表。 链表还包括更新的指示符。 对读取器进程的读取访问被提供给读取器进程，使得读取器进程根据三个内部列表的读取列表来访问链接列表中的元素。 将写入对链表的访问提供给写入器进程，使得写入器进程根据三个内部列表的写入列表访问链表中的元素。

公开(公告)号：US06651146B1

公开(公告)日：2003-11-18

申请号：US09513810

申请日：2000-02-24

申请人： Mysore Sathyanarayana Srinivas ,  James William Vanfleet ,  David Blair Whitworth

发明人： Mysore Sathyanarayana Srinivas ,  James William Vanfleet ,  David Blair Whitworth

IPC分类号： G06F1200

CPC分类号： G06F7/785 ,  G06F5/10 ,  G06F9/526 ,  G06F2205/064 ,  G06F2205/123 ,  Y10S707/99938

摘要： The present invention discloses a method of managing lists in a multiprocessor system without the use of locks that prevent contention for the list. List management in a linear list with a front and a back of the list has applications where it is desirable to manage the list in a Last In First Out (LIFO) and a First In First Out (FIFO) or a combination of LIFO and FIFO. LIFO and FIFO list management can be done by restrictively adding data elements to the front, back and removing data elements from the front of a managed list. At certain times there can be contention for a list and either locking routines are in place to prevent contention or some other method is used to guarantee data element integrity. The present invention discloses a set of operations that when used with certain protocols allow two or more processors to access a list as a LIFO or FIFO in a multiprocessor system without the use of locks.

摘要翻译： 本发明公开了一种在多处理器系统中管理列表的方法，而不使用防止列表竞争的锁。 具有列表前面和后面的线性列表中的列表管理具有应用程序，其中希望以先出先出（LIFO）和先进先出（FIFO）或LIFO和FIFO的组合来管理列表 。 LIFO和FIFO列表管理可以通过限制性地将数据元素添加到前端，后端和从托管列表的前面移除数据元素来完成。 在某些时候，可能会有一个列表的争用，并且锁定例程已经到位以防止争用，或者使用其他一些方法来保证数据元素的完整性。 本发明公开了一组操作，当与某些协议一起使用时，允许两个或多个处理器在不使用锁的情况下在多处理器系统中作为LIFO或FIFO访问列表。

公开(公告)号：US20030093637A1

公开(公告)日：2003-05-15

申请号：US10003168

申请日：2001-11-14

发明人： Shao-Kuang Lee ,  Jen-Pin Su ,  Tsan-Hui Chen

IPC分类号： G06F013/00

CPC分类号： G06F5/12 ,  G06F2205/123

摘要： A mechanism for maintaining the first-in first-out order of commands in a multiple-input and multiple-output buffer structure includes a command number generator for generating and assigning a command number to each command entering the buffer structure, and a command number comparator for comparing the command number of the outgoing command at each buffer in the buffer structure to determine which command should exit. Both command number generator and command comparator have a cyclic counter that has a period greater than or equal to the total number of allowable buffer entries in the buffer structure. For maintaining order of posted and non-posted command queues, a pending posted write counter is used in the posted command queue to record the number of pending posted write command and each entry in the non-posted command queue is associated with a dependency counter.

摘要翻译： 用于在多输入和多输出缓冲器结构中维持先进先出命令的机制包括：命令编号发生器，用于产生和分配命令号到进入缓冲器结构的每个命令，命令编号比较器 用于比较缓冲结构中每个缓冲区的输出命令的命令编号，以确定哪个命令应该退出。 命令编号发生器和命令比较器都具有循环计数器，其周期大于或等于缓冲器结构中允许的缓冲器条目的总数。 为了维护发布和未发布的命令队列的顺序，在发布的命令队列中使用挂起的写入计数器来记录挂起的写入命令的数量，并且非发布的命令队列中的每个条目与依赖关系计数器相关联。

公开(公告)号：US06266746B1

公开(公告)日：2001-07-24

申请号：US09120277

申请日：1998-07-22

申请人： Tomoaki Ando

发明人： Tomoaki Ando

IPC分类号： G06F1200

CPC分类号： G06F5/12 ,  G06F5/10 ,  G06F5/14 ,  G06F2205/123 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C8/00

摘要： A control apparatus controls writing and reading of data with respect to a memory which is randomly accessible. An address producing device produces an address by a method according to a predetermined rule, in response to a request to access the memory by the method according to the predetermined rule. A switching device selects one of an address with which the memory is randomly accessed and the address produced by the address producing device. Data is written into and read from the memory, at a location that corresponds to the address that is selected by the switching device and supplied to the memory. It is advantageous to provide a control device which supplies a switching signal to the switching device to cause the switching device to select one of the address with which the memory is randomly accessed and the address produced by the address producing device, depending upon the presence of a request to access the memory by the method according to the predetermined rule and the presence of a request to randomly access the memory.

摘要翻译： 控制装置控制对可随机访问的存储器的数据的写入和读取。 响应于通过根据预定规则的方法访问存储器的请求，地址产生设备通过根据预定规则的方法产生地址。 切换装置选择随机访问存储器的地址和由地址产生装置产生的地址之一。 在对应于由切换设备选择并提供给存储器的地址的位置处，将数据写入和读取存储器。 有利的是提供一种控制装置，该控制装置向切换装置提供切换信号，以使开关装置根据存在的方式选择存储器随机存取的地址和地址产生装置产生的地址 通过根据预定规则的方法访问存储器的请求以及随机访问存储器的请求的存在。

公开(公告)号：US06134155A

公开(公告)日：2000-10-17

申请号：US407156

申请日：1999-09-28

申请人： Sheung-Fan Wen

发明人： Sheung-Fan Wen

IPC分类号： G11C7/00 ,  G06F5/10 ,  G06F5/12 ,  G11C7/10

CPC分类号： G06F5/12 ,  G11C7/1051 ,  G11C7/1075 ,  G11C7/1078 ,  G06F2205/123

摘要： A FIFO stack is implemented using a DPRAM. One of the ports of the DPRAM is used to add elements to the FIFO stack, and the other port is used to remove elements from the FIFO stack. The ports operate in separate clock domains. A synchronization circuit coordinates the read and write operations across the clock domains.

摘要翻译： 使用DPRAM实现FIFO堆栈。 DPRAM的一个端口用于向FIFO堆栈添加元素，另一个端口用于从FIFO堆栈中删除元素。 这些端口在不同的时钟域中工作。 同步电路协调跨时钟域的读写操作。

公开(公告)号：US5719644A

公开(公告)日：1998-02-17

申请号：US521410

申请日：1995-08-30

申请人： Ki-Bok Park

发明人： Ki-Bok Park

IPC分类号： G06F5/10 ,  G06F5/12 ,  H04N5/907

CPC分类号： G06F5/12 ,  H04N5/907 ,  G06F2205/123

摘要： A data collision avoidance circuit is utilized in a memory write control circuit of an image signal processing apparatus for preventing the write and read clocks of a FIFO memory from colliding. The circuit contains a write enable signal generating unit, a window pulse section set up unit, and a write enable signal control unit. The write enable signal generating unit generates a write enable signal in response to the write control odd/even field signal to write the data into the FIFO memory. The window pulse section set up unit generates a window pulse signal having a predetermined pulse width. The time interval of the predetermined pulse width is designed to be greater than a time interval during which write and read clocks of the FIFO memory can potentially collide, and the window pulse signal is generated in response to a read control odd/even field signal. The write enable signal control unit is designed to suppress the write enable signal generated by the write enable signal generating unit in response to a predetermined edge of the write control odd/even field signal during the window pulse signal. As a result, the collision of the write and read clocks is prevented.

摘要翻译： 数据冲突避免电路用于图像信号处理装置的存储器写入控制电路，用于防止FIFO存储器的写入和读取时钟相互冲突。 该电路包括写入使能信号产生单元，窗口脉冲部分设置单元和写入使能信号控制单元。 写入使能信号生成单元响应于写入控制奇数/偶数场信号产生写入使能信号，以将数据写入FIFO存储器。 窗口脉冲部分设置单元产生具有预定脉冲宽度的窗口脉冲信号。 预定脉冲宽度的时间间隔被设计为大于FIFO存储器的写入和读取时钟可能发生碰撞的时间间隔，并且窗口脉冲信号响应于读取控制奇数/偶数场信号而产生。 写入使能信号控制单元被设计为在窗口脉冲信号期间响应于写入控制奇数/偶数场信号的预定边沿来抑制由写入使能信号产生单元产生的写使能信号。 结果，防止写和读时钟的冲突。

公开(公告)号：US5214783A

公开(公告)日：1993-05-25

申请号：US564900

申请日：1990-08-09

申请人： Jean-Pierre Lips ,  Jean-Marc Millet ,  Bernard Naudin

发明人： Jean-Pierre Lips ,  Jean-Marc Millet ,  Bernard Naudin

IPC分类号： G06F12/02 ,  G06F5/10 ,  G06F5/12 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F5/12 ,  G06F2205/064 ,  G06F2205/123

摘要： The subject device manages the access to message queues in a memory (6) by an enqueuer 2 and a dequeuer 7 when the enqueuer has priority over the dequeuer. It solves the contention problem raised when the dequeuer dequeues the last message from a queue while the enqueuer is enqueuing anew one. A queue control block QCB and queue status bits E, A, D are assigned to each queue and stored in memories 20 and 22. Each time dequeuer 7 performs a dequeuing operation it sets its D bit (dequeuer active) before updating the queue head field in the QCB block. When the enqueuer performs an enqueuing operation it sets an abort bit A, if it finds the D bit active and E bit active indicating that the queue contains at least one message to warn the dequeuer that it has to abort its process if it is dequeuing the last message from the queue.