公开(公告)号：US11929762B2

公开(公告)日：2024-03-12

申请号：US17878431

申请日：2022-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangseok Lee ,  Geunyeong Yu ,  Youngjun Hwang ,  Hongrak Son ,  Junho Shin ,  Bohwan Jun ,  Hyunseung Han

IPC: H03M13/11

CPC classification number: H03M13/1137 ,  H03M13/112 ,  H03M13/1134

Abstract: A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.

公开(公告)号：US11575502B2

公开(公告)日：2023-02-07

申请号：US17115161

申请日：2020-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wijik Lee ,  Youngsik Moon ,  Hongrak Son ,  Jaehun Jang

IPC: H04L9/00 ,  H04L9/30 ,  G06F21/60 ,  G06K9/62 ,  G06N3/04 ,  G06N3/08 ,  G06F12/10 ,  H04L9/14

Abstract: A homomorphic encryption processing device includes the processing circuitry is configured to generate ciphertext operation level information based on field information. The field information represents a technology field to which homomorphic encryption processing is applied. The ciphertext operation level information represents a maximum number of multiplication operations between homomorphic ciphertexts without a bootstrapping process. The processing circuitry is further configured to select and output a homomorphic encryption parameter based on the ciphertext operation level information. The processing circuitry is further configured to perform one of a homomorphic encryption, a homomorphic decryption and a homomorphic operation, based on the homomorphic encryption parameter. The homomorphic encryption processing device may adaptively generate a homomorphic encryption parameter according to a ciphertext operation level information determined based on a field information, and may perform a homomorphic encryption, a homomorphic decryption and a homomorphic operation based on the homomorphic encryption parameter.

公开(公告)号：US11539504B2

公开(公告)日：2022-12-27

申请号：US17336625

申请日：2021-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanbyeul Na ,  Sumin Kim ,  Hongrak Son ,  Junho Shin

IPC: H04L9/00 ,  H04L9/30 ,  H04L9/08 ,  G06F7/46

Abstract: A homomorphic operation accelerator includes a plurality of circuits and a homomorphic operation managing circuit. The plurality of circuits may perform homomorphic operations. The homomorphic operation managing circuit may receive cipher text data, homomorphic encryption information and homomorphic operation information from an external device. The homomorphic operation managing circuit may activate or deactivate each of a plurality of enable signals applied to the plurality of circuits based on the homomorphic encryption information and the homomorphic operation information. The homomorphic operation managing circuit may activate or deactivate each of the plurality of circuits based on the plurality of enable signals. The homomorphic encryption information may be associated with a homomorphic encryption algorithm used to generate the cipher text data. The homomorphic operation information may be associated with the homomorphic operations to be performed on the cipher text data.

公开(公告)号：US20220021515A1

公开(公告)日：2022-01-20

申请号：US17167203

申请日：2021-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehun Jang ,  Youngsik Moon ,  Wijik Lee ,  Hongrak Son

IPC: H04L9/00 ,  H04L9/08

Abstract: A client system includes a client-side host device, and a client-side storage device including a storage controller and a storage memory. The storage controller includes a host interface, a processor configured to control a read operation and a write operation for the storage memory, and a homomorphic encryption and decryption accelerator configured to, based on receiving a read request from the client-side host device, perform homomorphic encryption on first plaintext data that is read from the storage memory, to generate first homomorphic ciphertext data, and provide the first homomorphic ciphertext data to the client-side host device through the host interface, and based on receiving a write request from the client-side host device, perform homomorphic decryption on second homomorphic ciphertext data that is received through the host interface, to generate second plaintext data, and write the second plaintext data in the storage memory.

公开(公告)号：US20210224152A1

公开(公告)日：2021-07-22

申请号：US17018763

申请日：2020-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HANBYEUL NA ,  Jaehun Jang ,  Hongrak Son

IPC: G06F11/10 ,  G06F11/07

Abstract: A storage controller includes parallel input channels configured for simultaneously receiving data from substantially redundant memories, an error estimation unit, a decision unit, an error correction unit and a selection unit. The error estimation unit generates error information by estimating an error level of the plurality of data. The decision unit performs a logical operation on the plurality of data to generate operation data. The error correction unit generates error correction data by correcting an error of the operation data. The selection unit selects one of the operation data or the error correction data based on the error information.