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公开(公告)号：US11620505B2
公开(公告)日：2023-04-04
申请号：US16881963
申请日：2020-05-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaehun Jang , Hongrak Son , Changkyu Seol , Pilsang Yoon , Junghyun Hong
Abstract: A neuromorphic package device includes a systolic array package and a controller. The systolic array package includes neuromorphic chips arranged in a systolic array along a first direction and a second direction. The controller communicates with a host controls the neuromorphic chips. Each of the neuromorphic chips sequentially transfers weights of a plurality layers of a neural network system in the first direction to store the weights. A first neuromorphic chip performs a calculation based on stored weights therein and an input data received in the second direction, and provides a result of the calculation to at least one of a second neuromorphic chip and a third neuromorphic chip which are adjacent to the first neuromorphic chip. The at least one of the second and third neuromorphic chips performs a calculation based on a provided result of the calculation and stored weights therein.
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公开(公告)号：US11468306B2
公开(公告)日：2022-10-11
申请号：US16906209
申请日：2020-06-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaehun Jang , Hongrak Son , Changkyu Seol , Hyejeong So , Hwaseok Oh , Pilsang Yoon , Jinsoo Lim
Abstract: A storage system includes a host device and a storage device. The host device provides first input data for data storage function and second input data for artificial intelligence (AI) function. The storage device stores the first input data from the host device, and performs AI calculation based on the second input data to generate calculation result data. The storage device includes a first processor, a first nonvolatile memory, a second processor and a second nonvolatile memory. The first processor controls an operation of the storage device. The first nonvolatile memory stores the first input data. The second processor performs the AI calculation, and is distinguished from the first processor. The second nonvolatile memory stores weight data associated with the AI calculation, and is distinguished from the first nonvolatile memory.
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公开(公告)号：US11456048B2
公开(公告)日：2022-09-27
申请号：US17392781
申请日：2021-08-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jongyoon Yoon , Hyeonjong Song , Seonghyeog Choi , Hongrak Son
Abstract: In a method of predicting a remaining lifetime of the nonvolatile memory device, a read sequence is performed. The read sequence includes a plurality of read operations, and at least one of the plurality of read operations is sequentially performed until read data stored in the nonvolatile memory device is successfully retrieved. Sequence class and error correction code (ECC) decoding information are generated. A life stage of the nonvolatile memory device is determined based on at least one of the sequence class and the ECC decoding information. When it is determined that the nonvolatile memory device corresponds to a first life stage, a coarse prediction on the remaining lifetime of the nonvolatile memory device is performed. When it is determined that the nonvolatile memory device corresponds to a second life stage after the first life stage, a fine prediction on the remaining lifetime of the nonvolatile memory device is performed.
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公开(公告)号：US11436081B2
公开(公告)日：2022-09-06
申请号：US17018763
申请日：2020-09-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hanbyeul Na , Jaehun Jang , Hongrak Son
Abstract: A storage controller includes parallel input channels configured for simultaneously receiving data from substantially redundant memories, an error estimation unit, a decision unit, an error correction unit and a selection unit. The error estimation unit generates error information by estimating an error level of the plurality of data. The decision unit performs a logical operation on the plurality of data to generate operation data. The error correction unit generates error correction data by correcting an error of the operation data. The selection unit selects one of the operation data or the error correction data based on the error information.
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公开(公告)号：US11249848B2
公开(公告)日：2022-02-15
申请号：US17134961
申请日：2020-12-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngjun Hwang , Hongrak Son , Dongmin Shin
Abstract: An error check code (ECC) decoder includes a buffer, a data converter and a decoding circuit. The buffer stores a plurality of read pages read from a plurality of multi-level cells connected to a same wordline. The data converter adjusts reliability parameters of read bits of the plurality of read pages based on state-bit mapping information and the plurality of read pages to generate a plurality of ECC input data respectively corresponding to the plurality of read pages. The state-bit mapping information indicate mapping relationships between states and bits stored in the plurality of multi-level cells. The decoding circuit performs an ECC decoding operation with respect to the plurality of read pages based on the plurality of ECC input data. An error correction probability is increased by adjusting the reliability parameters of read bits based on the state-bit mapping information.
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Patent Agency Ranking
公开(公告)号：US12100465B2
公开(公告)日：2024-09-24
申请号：US17847744
申请日：2022-06-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngjun Hwang , Hongrak Son , Geunyeong Yu
CPC classification number: G11C29/52 , G11C7/1039 , G11C7/222 , G11C29/023
Abstract: Various example embodiments of the inventive concepts provide an error correction circuit and a semiconductor device. The error correction circuit includes clock-sync distributor circuitry configured to output a plurality of distributor output data based on distributor reception data received using a first clock signal, each of the plurality of distributor output data output based on the first clock signal or a second clock signal, the second clock signal having a higher frequency than a frequency of the first clock signal, a node processor configured to generate a plurality of output data by performing error correction decoding using the plurality of distributor output data, output a first subset of the plurality of output data based on the first clock signal, and output a second subset of the plurality of output data based on the second clock signal, and clock-sync combiner circuitry configured to output, based on the first clock signal, the plurality of output data received from the node processor.
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公开(公告)号：US12080366B2
公开(公告)日：2024-09-03
申请号：US17854638
申请日：2022-06-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kangseok Lee , Geunyeong Yu , Seonghyeog Choi , Hongrak Son , Youngjun Hwang
CPC classification number: G11C29/52 , G11C29/021 , G11C29/022
Abstract: In a method of error correction code (ECC) decoding, normal read data are read from a nonvolatile memory device based on normal read voltages, and a first ECC decoding is performed with respect to the normal read data. When the first ECC decoding results in failure, flip read data are read from the nonvolatile memory device based on flip read voltages corresponding to a flip range of a threshold voltage. Corrected read data are generated based on the flip read data by inverting error candidate bits included in the flip range among bits of the normal read data, and a second ECC decoding is performed with respect to the corrected read voltage. Error correction capability may be enhanced by retrying ECC decoding based on the corrected read data when ECC decoding based on the normal read data results in failure.
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公开(公告)号：US12067287B2
公开(公告)日：2024-08-20
申请号：US17685024
申请日：2022-03-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwanwoo Noh , Hyeonjong Song , Wijik Lee , Hongrak Son , Dongmin Shin , Seonghyeog Choi
CPC classification number: G06F3/0658 , G06F3/0614 , G06F3/0679 , G11C16/0483
Abstract: Provided are a memory controller calculating an optimal read level, a memory system including the memory controller, and an operating method of the memory controller. The memory controller includes: a processor configured to control a memory operation on the memory device; and a read level calculation module configured to: receive N counting values corresponding to N read levels generated based on a counting operation on data read by using a plurality of read levels, model at least two cell count functions having selected read levels that are selected from the N read levels as inputs, and the N counting values corresponding to the selected read levels as outputs, and calculate an optimal read level based on an optimal cell count function selected from the at least two cell count functions, wherein N is an integer equal to or greater than four, wherein the N counting values include counting values corresponding to at least four different read levels.
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公开(公告)号：US11483128B2
公开(公告)日：2022-10-25
申请号：US17126935
申请日：2020-12-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngsik Moon , Hongrak Son
Abstract: A homomorphic encryption device includes: a recryption parameter generating circuit, a recryption circuit, and an arithmetic circuit. The recryption parameter generating circuit is configured to generate a recryption parameter including a plurality of recryption levels respectively for a plurality of ciphertexts based on an arithmetic scenario including information about an arithmetic schedule between the plurality of ciphertexts. The recryption circuit is configured to generate a plurality of recrypted ciphertexts by recrypting each of the plurality of ciphertexts to a corresponding recryption level based on the recryption parameter. The arithmetic circuit is configured to output an arithmetic result by performing operations by using the plurality of recrypted ciphertexts, according to the arithmetic scenario.
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公开(公告)号：US11362868B2
公开(公告)日：2022-06-14
申请号：US16911801
申请日：2020-06-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Changkyu Seol , Hongrak Son , Geunyeong Yu , Pilsang Yoon , Jaehun Jang
Abstract: A neuromorphic device includes a neuron block, a spike transmission circuit and a spike reception circuit. The neuron block includes a plurality of neurons connected by a plurality of synapses to perform generation and operation of spikes. The spike transmission circuit generates a non-binary transmission signal based on a plurality of transmission spike signals output from the neuron block and transmits the non-binary transmission signal to a transfer channel, where the non-binary transmission signal includes information on transmission spikes included in the plurality of transmission spike signals. The spike reception circuit receives a non-binary reception signal from the transfer channel and generates a plurality of reception spike signals including reception spikes based on the non-binary reception signal to provide the plurality of reception spike signals to the neuron block, where the non-binary reception signal includes information on the reception spikes.
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