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公开(公告)号：US20210344205A1
公开(公告)日：2021-11-04
申请号：US17374840
申请日：2021-07-13
Applicant: STMicroelectronics Asia Pacific Pte Ltd.
Inventor： Yannick Guedon
Abstract: An over-voltage protection circuit and methods of operation are provided. In one embodiment, a method includes monitoring a voltage at an output of a rectifier, a voltage at an output of a voltage regulator, or a combination thereof. The method further includes determining the over-voltage condition based on the monitoring; and in response to determining the over-voltage condition, regulating the voltage at the output of the rectifier in accordance with a voltage difference between the voltage at the output of the rectifier and the voltage at the output of the voltage regulator.
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公开(公告)号：US11095146B2
公开(公告)日：2021-08-17
申请号：US16413283
申请日：2019-05-15
Applicant: STMicroelectronics Asia Pacific Pte Ltd.
Inventor： Yannick Guedon
Abstract: An over-voltage protection circuit and methods of operation are provided. In one embodiment, a method includes monitoring a voltage at an output of a rectifier, a voltage at an output of a voltage regulator, or a combination thereof. The method further includes determining the over-voltage condition based on the monitoring; and in response to determining the over-voltage condition, regulating the voltage at the output of the rectifier in accordance with a voltage difference between the voltage at the output of the rectifier and the voltage at the output of the voltage regulator.
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公开(公告)号：US20210135912A1
公开(公告)日：2021-05-06
申请号：US16669068
申请日：2019-10-30
Applicant: STMicroelectronics Asia Pacific Pte Ltd.
Inventor： Yannick Guedon
Abstract: A power transmitter includes: a first switch coupled between a first node and a reference voltage node; a second switch configured to be coupled between a power supply and the first node; a coil and a capacitor coupled in series between the first node and the reference voltage node; a first sample-and-hold (S&H) circuit having an input coupled to the first node; and a timing control circuit configured to generate a first control signal, a second control signal, and a third control signal that have a same frequency, where the first control signal is configured to turn ON and OFF the first switch alternately, the second control signal is configured to turn ON and OFF the second switch alternately, and where the third control signal determines a sampling time of the first S&H circuit and has a first pre-determined delay from a first edge of the first control signal.
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公开(公告)号：US10540040B2
公开(公告)日：2020-01-21
申请号：US15199332
申请日：2016-06-30
Applicant: STMICROELECTRONICS ASIA PACIFIC PTE LTD
Inventor： Yannick Guedon
IPC: G06F3/041 , G06F1/32 , G06F3/044 , G06F1/16 , G06F1/3234
Abstract: Dual power supply and energy recovery techniques are used in a capacitive touch panel that employs a concurrent drive scheme. A dual supply output buffer boosts a capacitor from an intermediate voltage level to a high voltage level. Energy recovery exchanges stored energy between a capacitor and an inductor. When both techniques are used together, power consumption of a capacitive touch panel drive circuit can be reduced dramatically, by as much as about 80%. Such high efficiency touch panels have wide application to ultra-thin touch screens, including those suitable for use in mobile devices and flexible displays.
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公开(公告)号：US10534489B2
公开(公告)日：2020-01-14
申请号：US15838675
申请日：2017-12-12
Applicant: STMicroelectronics Asia Pacific Pte Ltd
Inventor： Chee Weng Cheong , Dianbo Guo , Kien Beng Tan , Yannick Guedon
Abstract: A capacitive discharge circuit includes a line having a capacitance, a switched capacitor circuit including a capacitor, a switched circuit coupled to the line, and a voltage regulator coupled between the switched capacitor circuit and the switched circuit. A controller operates the switched capacitor circuit and switched circuit to in a first phase, charge the capacitor by coupling the capacitor between a common mode and a power supply, and in a second phase, discharge the capacitor by coupling the voltage regulator in series with the capacitor between the power supply node a ground. The controller is also configured to in a third phase, charge the capacitor by coupling the capacitor between the common mode and the power supply, and in a fourth phase, share charge between the line and the capacitor by coupling the voltage regulator and the capacitor in series between the line and the ground.
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Patent Agency Ranking
公开(公告)号：US09870113B2
公开(公告)日：2018-01-16
申请号：US15679771
申请日：2017-08-17
Applicant: STMicroelectronics Asia Pacific Pte Ltd
Inventor： Chee Weng Cheong , Dianbo Guo , Kien Beng Tan , Yannick Guedon
CPC classification number: G06F3/044 , G06F3/041 , G06F3/0418
Abstract: A capacitive discharge circuit includes a line having a capacitance, a switched capacitor circuit including a capacitor, a switched circuit coupled to the line, and a voltage regulator coupled between the switched capacitor circuit and the switched circuit. A controller operates the switched capacitor circuit and switched circuit to in a first phase, charge the capacitor by coupling the capacitor between a common mode and a power supply, and in a second phase, discharge the capacitor by coupling the voltage regulator in series with the capacitor between the power supply node a ground. The controller is also configured to in a third phase, charge the capacitor by coupling the capacitor between the common mode and the power supply, and in a fourth phase, share charge between the line and the capacitor by coupling the voltage regulator and the capacitor in series between the line and the ground.
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公开(公告)号：US09772726B2
公开(公告)日：2017-09-26
申请号：US14531631
申请日：2014-11-03
Applicant: STMicroelectronics Asia Pacific Pte Ltd
Inventor： Chee Weng Cheong , Dianbo Guo , Kien Beng Tan , Yannick Guedon
CPC classification number: G06F3/044 , G06F3/041 , G06F3/0418
Abstract: A capacitive discharge circuit includes a line having a capacitance, a switched capacitor circuit including a capacitor, a switched circuit coupled to the line, and a voltage regulator coupled between the switched capacitor circuit and the switched circuit. A controller operates the switched capacitor circuit and switched circuit to in a first phase, charge the capacitor by coupling the capacitor between a common mode and a power supply, and in a second phase, discharge the capacitor by coupling the voltage regulator in series with the capacitor between the power supply node a ground. The controller is also configured to in a third phase, charge the capacitor by coupling the capacitor between the common mode and the power supply, and in a fourth phase, share charge between the line and the capacitor by coupling the voltage regulator and the capacitor in series between the line and the ground.
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公开(公告)号：US09665215B2
公开(公告)日：2017-05-30
申请号：US13853887
申请日：2013-03-29
Applicant: STMicroelectronics Asia Pacific Pte. Ltd.
Inventor： Sze-Kwang Tan , Yannick Guedon
CPC classification number: G06F3/044 , G06F3/0418
Abstract: Apparatus and methods to measure capacitance changes for a touch-sensitive capacitive matrix are described. Charge-removal circuits and measurement techniques may be employed to cancel deleterious effects of parasitic capacitances in the touch-sensitive capacitive matrix. Capacitively switching a supply during timed charge removal may be used to cancel unwanted effects due to clock jitter. The apparatus and methods can improve signal-to-noise characteristics, sensitivity, and/or dynamic range for capacitive measurements relating to touch-sensitive capacitive devices.
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公开(公告)号：US20160077634A1
公开(公告)日：2016-03-17
申请号：US14945620
申请日：2015-11-19
Applicant: STMicroelectronics Asia Pacific Pte Ltd
Inventor： Yannick Guedon , Sze-Kwang Tan , Dianbo Guo
CPC classification number: G06F3/044 , G06F3/0414 , G06F3/0416 , G06F2203/04103 , G06F2203/04108
Abstract: A readout device for a capacitive sense matrix includes a computer readable storage medium configured to store capacitance data. The capacitance data represents capacitance values of the capacitive sense matrix. The readout device also includes a readout circuit configured to receive a signal from the capacitive sense matrix, the readout circuit being configured based upon the capacitance data. Also described are a readout method and a method of compensating for variations in capacitance.
Abstract translation: 用于电容性感测矩阵的读出装置包括被配置为存储电容数据的计算机可读存储介质。 电容数据表示电容性感测矩阵的电容值。 读出装置还包括被配置为从电容性感测矩阵接收信号的读出电路，读出电路基于电容数据配置。 还描述了补偿电容变化的读出方法和方法。
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公开(公告)号：US09235300B2
公开(公告)日：2016-01-12
申请号：US13853870
申请日：2013-03-29
Inventor： Paolo Angelini , Yannick Guedon , Ming Zi Zhu
CPC classification number: G06F3/044 , G03G7/00 , G06F3/0418 , G06G7/00
Abstract: Accumulators that operate to fully or partially remove noise from a signal, including removing noise inserted into the signal by the accumulator itself. In some embodiments, an accumulator may be operated in a sampling phase and a transfer phase each time the accumulator samples an input signal. In some such embodiments, an op-amp of an accumulation circuit of the accumulator may be auto-zeroed during some or all of the sampling phases of an accumulation period. In some embodiments in which the op-amp is auto-zeroed during some or all of the sampling phases, the accumulation circuit may include a holding capacitor that, during an auto-zeroing process, holds a value output by the op-amp during a prior transfer phase. Including such a holding capacitor in an accumulator may reduce a voltage that the op-amp output rises following the auto-zero process, which may reduce a bandwidth and noise of the accumulation circuit.
Abstract translation: 用于完全或部分地从信号中去除噪声的累加器，包括消除蓄电池本身插入到信号中的噪声。 在一些实施例中，每当累加器对输入信号进行采样时，累加器可以在采样阶段和传送阶段中操作。 在一些这样的实施例中，累加器的累加电路的运算放大器可以在累积周期的某些或全部采样阶段期间自动归零。 在一些实施例中，在某些或所有采样相位期间运算放大器自动归零，其中累积电路可以包括保持电容器，其在自动归零过程期间保持由运算放大器输出的值 先前转移阶段。 在存储器中包括这种保持电容器可以降低运算放大器输出在自动归零过程之后上升的电压，这可以降低积累电路的带宽和噪声。
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