公开(公告)号：US20150086154A1

公开(公告)日：2015-03-26

申请号：US14494647

申请日：2014-09-24

Applicant: STMicroelectronics SA

Inventor： Pascal Fonteneau

IPC: G02B6/122 ,  H01L27/02 ,  H01L25/16

CPC classification number: G02B6/4275 ,  G02B6/122 ,  G02B6/428 ,  G02B2006/12061 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/60 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/167 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/87 ,  H01L2224/16235 ,  H01L2225/06534 ,  H01L2225/06572 ,  H01L2924/10253 ,  H01L2924/1431

Abstract: A device includes integrated circuit chips mounted on one another. At least one component for protecting elements of a second chip is formed in a first chip. The chips may be of the SOI type, with the first chip including a first SOI layer having a first thickness and the second chip including a second SOI layer having a second thickness smaller than the first thickness. The first chip including the component for protecting may include an optical waveguide with the component for protecting formed adjacent the optical waveguide.

Abstract translation: 一种装置包括彼此安装的集成电路芯片。 用于保护第二芯片的元件的至少一个部件形成在第一芯片中。 芯片可以是SOI型，其中第一芯片包括具有第一厚度的第一SOI层，第二芯片包括第二厚度小于第一厚度的第二SOI层。 包括用于保护的部件的第一芯片可以包括具有邻近光波导形成的用于保护的部件的光波导。

公开(公告)号：US20140017858A1

公开(公告)日：2014-01-16

申请号：US13933441

申请日：2013-07-02

Applicant: STMicroelectronics SA ,  Commissariat a l'energie atomique et aux energies alternatives

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L27/0255 ,  H01L27/0296 ,  H01L27/1207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a transistor, an UTBOX buried insulating layer disposed under it, a ground plane disposed under the layer, a well disposed under the plane, a first trench made at a periphery of the transistor and extending through the layer and into the well, a substrate situated under the well, a p-n diode made on a side of the transistor and comprising first and second zones of opposite doping, the first zone being configured for electrical connection to a first electrode of the transistor, wherein first and second zones are coplanar with the plane, a second trench for separating the first and second zones, the second trench extending through the layer into the plane and until a depth less than an interface between the plane and the well, and a third zone under the second trench forming a junction between the zones.

Abstract translation: 集成电路包括晶体管，设置在其下的UTBOX埋入绝缘层，设置在层下面的接地平面，布置在平面下的阱，在晶体管的周围形成并延伸穿过该层并进入阱的第一沟槽 位于阱下的衬底，在晶体管的一侧制成的pn二极管，其包括相反掺杂的第一和第二区，第一区被配置为电连接到晶体管的第一电极，其中第一和第二区是 与所述平面共面的第二沟槽，用于分离所述第一和第二区域的第二沟槽，所述第二沟槽延伸穿过所述层进入所述平面并且直到深度小于所述平面和所述阱之间的界面，以及在所述第二沟槽形成之下的第三区域 区域之间的连接处。

公开(公告)号：US20140017856A1

公开(公告)日：2014-01-16

申请号：US13933379

申请日：2013-07-02

Applicant: STMicroelectronics SA ,  Commissariat à I'ènergie atomique et aux energies alternatives

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L27/0296 ,  H01L27/0688 ,  H01L27/1207

Abstract: An integrated circuit features a FET, an UTBOX layer plumb with the FET, an underlayer ground plane with first doping plumb with the FET's gate and channel, first and second underlayer semiconducting elements, both plumb with the drain or source, electrodes in contact respectively with the ground plane and with the first element, one having first doping and being connected to a first voltage, the other having the first doping and connected to a second bias voltage different from the first, a semiconducting well having the second doping and plumb with the first ground plane and both elements, a first trench isolating the first FET from other components of the integrated circuit and extending through the layer into the well, and second and third trenches isolating the FET from the electrodes, and extending to a depth less than a plane/well interface.

Abstract translation: 集成电路具有FET，具有FET的UTBOX层铅垂，具有FET的栅极和沟道的第一掺杂铅垂的下层接地层，第一和第二下层半导体元件，两者均与漏极或源极接触，电极分别接触 接地平面和第一元件，一个具有第一掺杂并且连接到第一电压，另一个具有第一掺杂并且连接到不同于第一掺杂的第二偏置电压，具有第二掺杂和铅垂的半导体阱与 第一接地平面和两个元件，第一沟槽将第一FET与集成电路的其它部件隔离并延伸穿过该阱进入阱，第二和第三沟槽将FET与电极隔离，并延伸至小于 平面/井界面。

公开(公告)号：US20140017821A1

公开(公告)日：2014-01-16

申请号：US13932134

申请日：2013-07-01

Applicant: STMicroelectronics SA ,  Commissariat a l'energie atomique et aux energies alternatives

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L25/07

CPC classification number: H01L25/07 ,  H01L27/0262 ,  H01L27/1207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes four electronic components, a buried UTBOX layer under and plumb with the electronic components, and two pairs of oppositely doped ground planes plumb with corresponding components under the layer. A first isolation trench mutually isolates the ground planes from corresponding wells made plumb and in contact with the ground planes and exhibiting the first doping type. Bias electrodes contact respective wells and ground planes. One pair of electrodes is for connecting to a first bias voltage and the other pair is for connecting to a second bias voltage. Also included are a semiconductor substrate exhibiting the first type of doping and a deeply buried well exhibiting the second type of doping. The deeply buried well contacts the other wells and separates them from the substrate. Finally, a control electrode couples to the deeply buried well.

Abstract translation: 集成电路包括四个电子部件，在电子部件下方并且铅垂的埋入的UTBOX层和在层下方具有相应部件的两对相对掺杂的接地平面。 第一隔离沟槽将接地层与相应的铅垂阱相分离并与接地层接触并呈现出第一掺杂型。 偏置电极接触相应的阱和接地层。 一对电极用于连接到第一偏置电压，另一对电极用于连接到第二偏置电压。 还包括呈现第一类掺杂的半导体衬底和呈现第二类掺杂的深埋阱。 深埋的井与其他井接触并将其与基底分离。 最后，控制电极耦合到深埋井。