公开(公告)号：US20240347435A1

公开(公告)日：2024-10-17

申请号：US18748765

申请日：2024-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong Hwang ,  Kyounglim SUK ,  Seokhyun LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204

Abstract: A semiconductor package includes a semiconductor chip, a lower redistribution layer disposed under the semiconductor chip, the lower redistribution layer including a plurality of lower insulating layers, a plurality of lower redistribution patterns, and a plurality of lower conductive vias, a lower passivation layer disposed under the lower redistribution layer and provided with a recess at a bottom surface of the lower passivation layer, an under bump metallization (UBM) pad disposed in the first recess, a UBM protective layer disposed in the first recess and connected to the lower conductive vias while covering a top surface and opposite side surfaces of the UBM pad, and an outer connecting terminal connected to a bottom surface of the UBM pad. The bottom surface of the UBM pad is positioned at a first depth from the bottom surface of the lower passivation layer.

公开(公告)号：US20240321815A1

公开(公告)日：2024-09-26

申请号：US18735408

申请日：2024-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soohyun NAM ,  Younglyong KIM

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/73 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0655 ,  H01L2224/16235 ,  H01L2224/32056 ,  H01L2224/32059 ,  H01L2224/32235 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/3512

Abstract: A semiconductor package including an interposer substrate, first to third semiconductor chips on the interposer substrate to face each other, an underfill part between each of the first to third semiconductor chips and the interposer substrate, a first side-fill part extending upward from a lower end of side walls of the first to third semiconductor chips, and a second side-fill part between the side walls of the first to third semiconductor chips and extending from the first side-fill part to an upper end of the side walls of the first to third semiconductor chips may be provided.

公开(公告)号：US20240321660A1

公开(公告)日：2024-09-26

申请号：US18188577

申请日：2023-03-23

Applicant: Intel Corporation

Inventor： Shakul Tandon

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/532 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/3107 ,  H01L21/56 ,  H01L23/49827 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/182

Abstract: Embodiments of semiconductor devices with stitched guard rings, along with methods and lithographic reticles for forming the same, are disclosed herein. In one example, a semiconductor die includes a substrate with integrated circuitry, and a guard ring surrounding the integrated circuitry. The guard ring includes traces arranged in a pattern of lines and rungs, where the lines extend around the integrated circuitry and the rungs extend crosswise between at least some of the lines.

公开(公告)号：US12100611B2

公开(公告)日：2024-09-24

申请号：US18389577

申请日：2023-11-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H10B20/20

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H10B12/05 ,  H10B20/20

Abstract: A method for producing 3D semiconductor devices including: providing a first level including first transistors and a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one second level on top of or above the second metal layer; performing a lithography step on the second level; forming at least one third level on top of or above the second level; performing processing steps to form first memory cells within the second level and second memory cells within the third level, where the first memory cells include at least one second transistor, the second memory cells include at least one third transistor, second transistors comprise gate electrodes comprising metal, and then forming at least four independent memory arrays which include some first memory cells and/or second memory cells.

公开(公告)号：US20240312864A1

公开(公告)日：2024-09-19

申请号：US18676343

申请日：2024-05-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Yin Hsieh ,  Li-Hui Cheng ,  Pu Wang ,  Szu-Wei Lu

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/42 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/3675 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/42 ,  H01L23/49827 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16235 ,  H01L2924/1715

Abstract: A manufacturing method of a package structure includes: coupling a device package to a package substrate, where the device package includes semiconductor dies encapsulated by an insulating encapsulation and electrically coupled to the package substrate; forming a first dielectric pattern on the device package opposite to the package substrate, where the first dielectric pattern includes openings corresponding to the semiconductor dies of the device package; forming a thermal conductive material on the semiconductor dies of the device package and in the openings of the first dielectric pattern; placing a heat dissipating component over the device package and the package substrate, the heat dissipating component being in contact with the first dielectric pattern and the thermal conductive material; and performing a thermal treatment process on the first dielectric pattern and the thermal conductive material to form a thermal interface material structure coupling the heat dissipating component to the device package.

公开(公告)号：US20240250035A1

公开(公告)日：2024-07-25

申请号：US18098806

申请日：2023-01-19

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Se Hwan Hong ,  Min Su Jeong ,  Gam Han Yong ,  Won Chul Do ,  Ji Hun Lee ,  Jae Yoon Kim ,  Jin Hyuk Chang ,  Ji Yeon Ryu ,  Dong Hoon Han

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/60 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/544

CPC classification number: H01L23/5385 ,  H01L21/56 ,  H01L21/60 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5386 ,  H01L23/544 ,  H01L24/08 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L2021/60075 ,  H01L2021/6009 ,  H01L2224/08113 ,  H01L2224/16112 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17055 ,  H01L2224/32059 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48225 ,  H01L2924/1016 ,  H01L2924/1811 ,  H01L2924/182

Abstract: In one example, an electronic device includes a lower substrate comprising a lower substrate upper side and a lower substrate lower side, and an upper substrate comprising an upper substrate upper side and an upper substrate lower side. The electronic device also includes a first electronic component and a second electronic component coupled to the upper substrate upper side. A first device interconnect and a second device interconnect couple the lower substrate upper side to the upper substrate lower side. The electronic device also includes a connect die coupled to the lower substrate upper side that electrically couples the first electronic component to the second electronic component. Other examples and related methods are also disclosed herein.

公开(公告)号：US12040264B2

公开(公告)日：2024-07-16

申请号：US17508250

申请日：2021-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong Hwang ,  Kyounglim Suk ,  Seokhyun Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204

Abstract: A semiconductor package includes a semiconductor chip, a lower redistribution layer disposed under the semiconductor chip, the lower redistribution layer including a plurality of lower insulating layers, a plurality of lower redistribution patterns, and a plurality of lower conductive vias, a lower passivation layer disposed under the lower redistribution layer and provided with a recess at a bottom surface of the lower passivation layer, an under bump metallization (UBM) pad disposed in the first recess, a UBM protective layer disposed in the first recess and connected to the lower conductive vias while covering a top surface and opposite side surfaces of the UBM pad, and an outer connecting terminal connected to a bottom surface of the UBM pad. The bottom surface of the UBM pad is positioned at a first depth from the bottom surface of the lower passivation layer.

公开(公告)号：US12033973B2

公开(公告)日：2024-07-09

申请号：US17367995

申请日：2021-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soohyun Nam ,  Younglyong Kim

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/73 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0655 ,  H01L2224/16235 ,  H01L2224/32056 ,  H01L2224/32059 ,  H01L2224/32235 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/3512

Abstract: A semiconductor package including an interposer substrate, first to third semiconductor chips on the interposer substrate to face each other, an underfill part between each of the first to third semiconductor chips and the interposer substrate, a first side-fill part extending upward from a lower end of side walls of the first to third semiconductor chips, and a second side-fill part between the side walls of the first to third semiconductor chips and extending from the first side-fill part to an upper end of the side walls of the first to third semiconductor chips may be provided.

公开(公告)号：US12033884B2

公开(公告)日：2024-07-09

申请号：US18542983

申请日：2023-12-18

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/74 ,  G11C8/16 ,  H01L21/683 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H10B20/20

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H10B12/05 ,  H10B20/20

Abstract: A method for producing 3D semiconductor devices including: providing a first level including first transistors and a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one (ALO) second level on top of or above the second metal layer; performing a lithography step on the second level; forming ALO third level on top of or above the ALO second level; performing processing steps to form first memory cells within the ALO second level and second memory cells within the ALO third level, first memory cells include ALO second transistor, second memory cells include ALO third transistor, first metal layer thickness is at least 50% greater than the second metal layer thickness, ALO first transistor controls power delivery to ALO second transistor; then dicing using a laser system.

公开(公告)号：US20240213188A1

公开(公告)日：2024-06-27

申请号：US18542393

申请日：2023-12-15

Applicant: ANALOG DEVICES, INC.

Inventor： Santosh Anil Kudtarkar ,  Arun Raj ,  Sharad Vidyarthy ,  Thomas M. Goida

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498

CPC classification number: H01L23/66 ,  H01L23/3675 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/16 ,  H01L2223/6616 ,  H01L2224/08146 ,  H01L2224/08235 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/182

Abstract: An integrated device package may include a glass interposer having one or more conductive vias extending through the glass interposer from a top side of the glass interposer to a bottom side of the glass interposer, the bottom side of the glass interposer comprising one or more contact pads. The device package may include an integrated device die mounted and electrically connected to the top side of the glass interposer. The device package may also include an encapsulating material disposed over at least a side surface of the glass interposer, a portion of the top surface of the glass interposer, and a side surface of the integrated device die.